SiC Wafer FOUP Layout for 200 mm Transport Without Contact

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Solution Overview

Problem

Conventional transport carriers for silicon carbide semiconductor substrates with diameters of 200 mm or more are limited to accommodating a maximum of 25 substrates due to deformation and warpage issues, leading to poor manufacturability and potential substrate contact during transportation.

Innovation Solution

The use of a Front Opening Unified Pod (FOUP) as a transport carrier that can accommodate up to 25 silicon carbide semiconductor substrates with a diameter of 200 mm or more, featuring a partition portion with support points and a larger distance between substrates to prevent contact and enhance manufacturability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a standard mechanical interface (SMIF) is used as a transport carrier, then the housing size is compact and easy to handle, but the distance between accommodated SiC semiconductor substrates is short causing substrates to come into contact during transportation

Engineering Contradiction:
Improvehandling convenienceVSAvoidsubstrate contact prevention
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The transport carrier housing is divided into multiple compartments, with each compartment designed to accommodate a single SiC semiconductor substrate. This segmentation ensures that substrates are physically separated and cannot come into contact with each other during transportation, while still maintaining a compact overall housing structure for easy handling.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple SiC semiconductor substrates with diameter of 200 mm or more are transported in a compact carrier, then transportation efficiency is improved, but substrates come into contact and defects occur

Engineering Contradiction:
Improvetransportation efficiencyVSAvoidsubstrate defect prevention
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The carrier design utilizes three-dimensional space optimization by arranging substrates in multiple layers or levels within the housing. Support structures are positioned at specific heights and locations to maintain proper spacing between substrates in both horizontal and vertical dimensions, allowing maximum substrate capacity while preventing contact and defects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of operation

If the housing for accommodating SiC semiconductor substrates is made small, then the carrier is more compact and easier to handle, but 25 semiconductor substrates cannot be transported as one unit

Engineering Contradiction:
Improvecarrier portabilityVSAvoidsubstrate transport capacity
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The carrier employs a nested arrangement where substrates are positioned in concentric or layered patterns within the housing. Smaller substrates can be arranged around larger ones, or substrates are stacked in multiple levels with appropriate spacing, maximizing the use of available internal volume while maintaining compact external dimensions for easy handling.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20250279303A1Method of manufacturing semiconductor device
Publication Date: 2025.09.04 MITSUBISHI ELECTRIC CORP
  • US20250279303A1 patent drawing
  • US20250279303A1 patent drawing
  • US20250279303A1 patent drawing

AI summary

A method of manufacturing a semiconductor device includes a step of performing processing and a step of transporting. In the step of performing processing, processing for forming a semiconductor element is performed on a semiconductor substrate made from silicon carbide and having a diameter W of 200 mm or more. In the step of transporting, at least one of before and after processing, a semiconductor substrate is accommodated and transported in a FOUP, which is a transport carrier capable of accommodating a maximum of 25 semiconductor substrates.