SiC Epitaxial Wafer Impurity Control for Ultrahigh Breakdown Voltage
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Solution Overview
Problem
Existing silicon carbide semiconductor devices face challenges in achieving ultrahigh breakdown voltages due to high trap densities of titanium and chromium in the epitaxial layer, which affect the breakdown voltage, and existing methods struggle to accurately measure trap densities below 1.0×1014 cm−3.
Innovation Solution
The silicon carbide wafer and semiconductor device are designed with a trap density of 1.0×1013 cm−3 or less in the epitaxial layer, achieved by controlling titanium and chromium densities in the substrate and epitaxial layer to 1.0×1017 cm−3 or less, using SIMS and DLTS methods to ensure high reliability without increasing manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC wafers are used with standard epitaxial growth processes, then manufacturing simplicity is maintained, but trap density in the epitaxial layer remains high due to Ti and Cr impurities, limiting breakdown voltage performance
Solution Approach 1:
The patent applies parameter changes by strictly controlling the trap density parameter in the epitaxial layer to be 1.0×10^13 cm^-3 or less at activation energy of 0.10 to 0.20 eV. This involves adjusting growth conditions and substrate quality parameters during epitaxial growth to minimize Ti and Cr impurity incorporation, thereby achieving ultrahigh breakdown voltage while maintaining manufacturing feasibility
Solution Approach 2:
The patent extracts and removes harmful Ti and Cr impurities from the epitaxial layer by selecting substrates with Ti density of 1.0×10^17 cm^-3 or less and Cr density of 1.0×10^17 cm^-3 or less. The epitaxial growth process is optimized to prevent incorporation of these impurities, effectively extracting the harmful elements from the device structure
2Reliability
If substrate impurity levels are reduced to lower epitaxial layer trap density, then device reliability improves, but substrate selection and characterization complexity increases
Solution Approach 1:
The patent replaces complex post-growth purification processes with a preventive approach using substrate characterization techniques (SIMS method) before epitaxial growth. By measuring and selecting substrates with Ti density of 1.0×10^17 cm^-3 or less and Cr density of 1.0×10^17 cm^-3 or less, the process substitutes complex contamination control with simpler substrate selection and measurement procedures
Solution Approach 2:
The patent implements feedback control by using SIMS measurement results to guide substrate selection and adjust epitaxial growth parameters. The trap density measurement (1.0×10^13 cm^-3 or less) serves as feedback to verify whether the growth process successfully minimized impurity incorporation, allowing for process optimization
3Adaptability or versatility
If trap density is reduced to achieve ultrahigh breakdown voltage, then voltage range performance improves, but manufacturing process sensitivity increases
Solution Approach 1:
The patent applies preliminary action by pre-characterizing substrates using SIMS measurement to determine Ti and Cr density before initiating epitaxial growth. This preliminary selection of substrates with Ti density of 1.0×10^17 cm^-3 or less and Cr density of 1.0×10^17 cm^-3 or less prevents impurity incorporation from the outset, making the manufacturing process more robust and less sensitive to variations during growth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the production of highly reliable silicon carbide semiconductor devices with ultrahigh breakdown voltages by effectively managing trap densities, ensuring consistent performance across various voltage ranges.
Implementation Method 1
The epitaxial layer has a trap density of 1.0×10^13 cm^-3 or less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method
Implementation Method 2
The substrate has a Ti density of 1.0×10^17 cm^-3 or less measured by a SIMS method and a Cr density of 1.0×10^17 cm^-3 or less measured by a SIMS method
Implementation Method 3
The SiC wafer is formed by growing an epitaxial layer of SiC on a substrate formed of SiC
Data Source
AI summary
A silicon carbide wafer includes: a substrate made of silicon carbide; and an epitaxial layer made of silicon carbide and arranged on the substrate. A chip formation region is defined in which a semiconductor element is formed, and an outer peripheral region is defined to surround the chip formation region. The epitaxial layer has a trap density of 1.0×1013 cm−3 or less at an activation energy of 0.10 to 0.20 eV derived by a DLTS method in the chip formation region. The substrate has a Ti density of 1.0×1017 cm−3 or less measured by a SIMS method and a Cr density of 1.0×1017 cm−3 or less measured by a SIMS method.