SiC Wafer Satin Back Surface and Mirror Main Surface Processing
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Solution Overview
Problem
The challenge lies in manufacturing high-quality silicon carbide (SiC) wafers with reduced material loss, as SiC wafers are difficult to process due to their hardness and brittleness, and existing methods struggle to remove the work-affected layer from the entire wafer surface, including outer peripheral portions and notches, which leads to defects and increased SORI values during high-temperature annealing.
Innovation Solution
A SiC wafer manufacturing method involving satin finishing of the back surface, followed by Si vapor pressure etching, and subsequent mirror processing of the main surface, using boron carbide or silicon carbide abrasive grains to achieve a roughness of 50-300 nm and 0.5-5 μm, effectively removing the work-affected layer and reducing material loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If diamond abrasive grains are used for surface processing to remove the work-affected layer, then the work-affected layer can be effectively removed, but the processing cost increases and material loss occurs
Solution Approach 1:
The patent replaces mechanical abrasion using diamond abrasive grains with a chemical etching process using KOH solution. This substitution eliminates the need for mechanical contact that causes material loss and surface damage, while effectively removing the work-affected layer through chemical dissolution. The etching process selectively removes damaged material without the collateral damage associated with abrasive mechanical processing.
Solution Approach 2:
The patent changes the processing parameters from mechanical (abrasive grain hardness, contact pressure) to chemical (etchant concentration, temperature, etching time). By controlling these chemical parameters, the work-affected layer is removed with precise depth control and minimal material loss, while maintaining surface integrity.
2Shape
If the back surface is made into a mirror surface like the main surface, then the wafer appearance is uniform, but it becomes difficult to distinguish the main surface from the back surface and increases slipping risk during conveyance
Solution Approach 1:
The patent intentionally creates asymmetry between the two wafer surfaces by making the main surface a mirror finish while making the back surface a satin finish. This asymmetric treatment provides visual distinction between surfaces for proper orientation during handling and processing, while the main surface maintains its high quality mirror finish for device manufacturing requirements.
Solution Approach 2:
The patent applies different surface quality standards to different locations of the wafer. The main surface receives high-quality mirror finishing suitable for semiconductor device fabrication, while the back surface receives satin finishing that provides tactile and visual identification cues without compromising the overall wafer quality.
3Ease of manufacture
If the work-affected layer is not removed, then the manufacturing process is simpler and material loss is reduced, but the SORI value increases during high-temperature annealing and cracks appear as defects
Solution Approach 1:
The patent performs preliminary removal of the work-affected layer before the high-temperature annealing process. By eliminating the damaged surface layer in advance through chemical etching, the subsequent annealing process operates on sound, defect-free material, preventing the formation of cracks and excessive SORI values that would occur if the damaged layer were present.
Solution Approach 2:
The patent applies preliminary anti-action by removing the problematic work-affected layer before it can cause harm during high-temperature processing. The chemical etching process preemptively eliminates the source of future defects (cracks and SORI issues) that would arise during annealing, thereby preventing reliability problems before they occur.
4Manufacturing precision
If SiC wafers are processed using conventional methods, then the work-affected layer can be removed from the main surface, but the outer peripheral portions and notches retain the work-affected layer leading to localized defects
Solution Approach 1:
The patent employs a universal chemical etching process that uniformly treats the entire wafer surface, including the outer peripheral portions and notches, without requiring separate processing steps for different regions. The KOH solution penetrates and etches the work-affected layer across all surfaces uniformly, ensuring consistent quality throughout the entire wafer structure.
Solution Approach 2:
The patent uses the KOH solution as an intermediary medium that can access and remove the work-affected layer from complex geometries including notches and peripheral regions. This liquid intermediary flows into all accessible areas, providing uniform etching action that mechanical methods cannot achieve in recessed or peripheral zones.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the detection rate of optical sensors, reduces material loss, and produces high-quality SiC wafers with minimal lattice strain and defects, allowing for more wafers to be produced from a single ingot with improved flatness and reduced processing costs.
Implementation Method 1
an etching technique (hereinafter, also referred to as Si vapor pressure etching) for etching a SiC wafer by heating the SiC wafer under Si vapor pressure
Data Source
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AI summary
An object is to provide a SiC wafer in which a detection rate of an optical sensor can improved and a SiC wafer manufacturing method. The method includes: a satin finishing process S141 of satin-finishing at least a back surface 22 of a SiC wafer 20; an etching process 21 of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure after the satin finishing process S141; and a mirror surface processing process S31 of mirror-processing a main surface 21 of the SiC wafer 20 after the etching process S21. Accordingly, it is possible to obtain a SiC wafer having the mirror-finished main surface 21 and the satin-finished back surface 22.