Silicon Carbide Wafer Scribe Line Adjustment for Defect Avoidance
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Solution Overview
Problem
In semiconductor manufacturing, especially for high-power silicon carbide and LED devices, defects on wafers are unevenly distributed, leading to defective devices due to the formation of surface defects during the single-crystal process, which existing defect covering methods are inefficient and costly, and affect the yield of semiconductor chips.
Innovation Solution
A method and apparatus for inspecting defects on silicon carbide wafers or epitaxial layers, using incident light to detect surface defects and adjust the position of scribe lines to maximize the number of dies avoided from defect locations, involving a lattice-shaped virtual scribe line and a comprehensive inspection apparatus with light condensing and detection units to identify and adjust die divisions based on defect coordinates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If defect covering methods are used to minimize wafer defects, then device defect rate decreases, but manufacturing cost increases and process efficiency decreases
Solution Approach 1:
The patent performs defect inspection and scribe line position adjustment before die formation and assembly. By identifying defect locations early and pre-adjusting the scribe line positions to avoid these defects, the method prevents defective devices from being formed in the first place, eliminating the need for costly post-manufacturing defect covering processes
Solution Approach 2:
The patent creates a virtual model of the wafer surface including defect locations, and uses this information to calculate and determine optimal scribe line positions that avoid defects. This virtual planning approach allows optimization of die layout without physical trial and error, reducing manufacturing costs while maintaining high device quality
2Productivity
If traditional fixed scribe line positions are used, then manufacturing process is simple, but number of functional dies decreases due to defect locations
Solution Approach 1:
The patent transitions from fixed, static scribe line positions to dynamic, adjustable scribe line positions that can be optimized based on actual defect locations. The system calculates optimal scribe line positions by considering defect coordinates and die layout, allowing the scribe lines to be dynamically repositioned to maximize the number of functional dies while maintaining manufacturing feasibility
Solution Approach 2:
The patent changes the positional parameters of scribe lines based on defect location data. By adjusting the coordinates and positions of scribe lines according to the distribution of surface defects, the system optimizes die yield without requiring complex physical modifications to the manufacturing process itself
3Reliability
If comprehensive defect inspection is performed to identify all surface defects, then device quality improves, but inspection time and complexity increase
Solution Approach 1:
The patent extracts only the critical information needed for scribe line optimization - specifically the coordinates and locations of surface defects that would affect die functionality. Rather than performing exhaustive analysis of all defect characteristics, the system focuses on extracting and utilizing only the spatial location data necessary for positioning scribe lines to avoid defects
Solution Approach 2:
The patent creates a simplified digital representation (copy) of the wafer surface containing defect location information, which is then used for calculating optimal scribe line positions. This virtual model allows rapid computation and optimization without requiring repeated physical inspection cycles, reducing inspection time while maintaining comprehensive defect detection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the impact of wafer defects on semiconductor chip yield by efficiently identifying and avoiding defect locations, thereby increasing the number of functional dies and improving manufacturing efficiency and economy.
Implementation Method 1
incident light having a predetermined cross-sectional bam size and wavelength is scanned onto the wafer surface to detect a reflected light reflected from the wafer surface
Implementation Method 2
detecting photoluminescence generated by scanning the incident light onto the wafer surface, identifying PL defect in the detected photoluminescence
Data Source
AI summary
The present invention relates to defects inspection on a silicon carbide wafer or an epitaxial layer thereon to determine the location, and adjustment of the location of the scribe line, which is a separation line forming a gap between adjacent dies. The present invention can obtain high efficiency and economy in the semiconductor process using wafers containing various defects in the surface and thin film, by minimizing the effect of wafer defects on the final yield of the semiconductor chip or die, via adjustment of scribe line positions arranged on the wafer.