SiC Epitaxial Wafer Defect Mapping via Stacking Fault Density

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Solution Overview

Problem

It is challenging to nondestructively check the position and number of basal plane dislocations in a SiC substrate after a SiC epitaxial layer is stacked, as these defects can cause killer defects in SiC devices.

Innovation Solution

A SiC epitaxial wafer is developed with a specific density range of basal plane dislocations in the substrate (1/cm2 to 3000/cm2) and controlled densities of double Shockley type stacking faults and other stacking faults in the epitaxial layer, allowing for estimation of basal plane dislocation positions and numbers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a SiC epitaxial layer is stacked on the SiC substrate, then the SiC epitaxial wafer can be used for semiconductor devices, but it becomes difficult to nondestructively check the position and number of basal plane dislocations in the substrate

Engineering Contradiction:
Improvedevice operation reliabilityVSAvoiddifficulty of detecting basal plane dislocations
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent uses stacking faults in the SiC epitaxial layer as an intermediary indicator to detect basal plane dislocations in the SiC substrate. By controlling and measuring the density of stacking faults (particularly double Shockley type stacking faults), the invention enables indirect detection of basal plane dislocation positions and numbers without requiring direct observation of the dislocations themselves, thus solving the detection difficulty while maintaining substrate reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent establishes a feedback mechanism where the density of stacking faults in the epitaxial layer provides information about the basal plane dislocation density in the substrate. By setting specific density ranges (1-3000/cm² for BPDs, 4-10/cm² for 2SSF, and ≤2/cm² for other stacking faults), the system uses the epitaxial layer characteristics to feedback on substrate quality, enabling nondestructive evaluation that ensures device reliability

Inventive Principle:
Principle #23Feedback

2Reliability

If the density of basal plane dislocations is reduced, then killer defects are reduced, but it becomes harder to estimate the position and number of remaining dislocations after epitaxial layer stacking

Engineering Contradiction:
Improvereduction of killer defectsVSAvoidloss of dislocation position and number information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent employs stacking faults as an intermediary that preserves information about basal plane dislocations even when dislocation density is reduced to safe levels. The stacking faults act as visible markers that correlate with the underlying dislocation structure, allowing estimation of position and number of remaining dislocations through nondestructive measurement of stacking fault density in the epitaxial layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention creates a copy of the dislocation information in the form of stacking faults within the epitaxial layer. These stacking faults replicate the spatial distribution and density characteristics of the basal plane dislocations in the substrate, providing a measurable surrogate that preserves the information needed for quality assessment even when the original dislocations are reduced to acceptable low levels

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables nondestructive estimation of basal plane dislocation concentrations and numbers in the SiC substrate even after the epitaxial layer is stacked, ensuring high-quality SiC epitaxial wafers with reduced device failure risks.

Implementation Method 1

a SiC epitaxial layer deposited on the SiC substrate

Methodology Applied
Scientific EffectEpitaxial deposition: Epitaxy

Data Source

PatentUS20250142910A1SiC EPITAXIAL WAFER
Publication Date: 2025.05.01 RESONAC CORP
  • US20250142910A1 patent drawing

AI summary

A SiC epitaxial wafer according to the present embodiment includes: a SiC substrate; and a SiC epitaxial layer deposited on the SiC substrate, wherein, in the SiC substrate, a density of basal plane dislocations is 1/cm2 or more and 3000/cm2 or less, and wherein, in the SiC epitaxial layer, a density of double Shockley (2SSF) type stacking faults is 4/cm2 or more and 10/cm2 or less, and a density of stacking faults other than the double Shockley (2SSF) type stacking faults is 2/cm2 or less.