SiC Wafer Residual Stress Balancing to Prevent Warpage
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Solution Overview
Problem
The manufacture of silicon-carbide wafers, particularly 3C-SiC wafers, is complex and prone to warpage, especially in larger dimensions, rendering them unusable for electronic devices.
Innovation Solution
A production process involving chemical vapor deposition (CVD) with controlled doping of N-type and P-type dopants during SiC layer growth to regulate tensile and compressive stresses, balancing residual stress in the wafer to prevent warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a SiC wafer is thinned to reduce parasitic capacitance and improve device performance, then device speed and integration density are improved, but residual stress increases causing wafer bending and breaking
Solution Approach 1:
The patent segments the wafer thinning process into multiple controlled stages with intermediate annealing treatments. Instead of thinning to the final thickness in one step, the wafer is thinned incrementally with stress-relief annealing performed at intermediate thicknesses, thereby managing residual stress accumulation and preventing wafer breakage while achieving the target thin thickness for high-speed device performance.
Solution Approach 2:
The patent changes the physical-chemical parameters of the wafer through controlled annealing treatments at specific temperatures (e.g., 1000-1500°C) in nitrogen or oxygen atmospheres. These parameter changes (temperature, atmosphere, time) modify the stress state and microstructure of the thinned wafer, relieving residual stress and preventing bending while maintaining the thin thickness required for high device speed and low parasitic capacitance.
2Quantity of substance
If conventional thinning processes are used to reduce wafer thickness, then parasitic capacitance is reduced, but stress concentration leads to wafer breaking
Solution Approach 1:
The patent applies preliminary stress-relief annealing treatments before completing the full thinning process. By performing annealing at intermediate stages while the wafer still has sufficient thickness to withstand handling, the wafer's stress state is preemptively managed, preventing stress concentration and breaking during subsequent thinning steps or device fabrication processes.
Solution Approach 2:
The patent introduces intermediate annealing steps that act as a cushioning mechanism against stress accumulation. These annealing treatments create a buffer by periodically relieving residual stress during the thinning process, preventing the build-up of critical stress levels that would lead to wafer breaking, thereby ensuring wafer reliability throughout the manufacturing process.
3Quantity of substance
If wafer thickness is reduced for higher device performance, then parasitic capacitance decreases, but manufacturing complexity increases due to stress control requirements
Solution Approach 1:
The patent implements periodic annealing treatments at regular intervals during the thinning process. This periodic action creates a standardized, repeatable manufacturing sequence (thin-anneal-thin-anneal) that, while adding steps, provides systematic stress control. The periodic nature makes the process more manageable and controllable compared to attempting to manage stress in a continuous or ad-hoc manner during thinning.
Solution Approach 2:
The patent integrates stress-relief annealing as continuous useful actions within the thinning process rather than separate corrective measures. By embedding annealing steps within the thinning sequence, the process continuously manages stress accumulation rather than allowing it to build up and then correcting it later, thereby reducing overall manufacturing complexity despite the additional thermal processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process results in flat silicon-carbide wafers with controlled residual stress, suitable for large dimensions, enabling their use in electronic device manufacturing without cracking or damage.
Implementation Method 1
forming a first epitaxial layer on the SiC substrate, wherein the first epitaxial layer comprises a first structured region and a first non-structured region
Implementation Method 2
forming a SiO2 insulation layer on the first epitaxial layer
Data Source
Figure 1~3
Figure 4~6
AI summary
A manufacturing method of a SiC wafer comprising the steps of: introducing a support (58) into a reaction chamber (24); forming a first SiC layer (60) on the support (58); separating the support (58) from the first SiC layer (60); and growing a second SiC layer (68) on the first SiC layer (60), including introducing into the reaction chamber (24) a precursor in the gaseous phase of a first dopant having a first electrical conductivity (N) and such as to generate a first stress in the second SiC layer (68); and introducing into the reaction chamber (24) a precursor in the gaseous phase of a second dopant having a second electrical conductivity (P) opposite to the first electrical conductivity (N), and such as to generate a second stress in the second SiC layer (68) that is opposite to, and balances, the first stress. The SiC wafer is thus without effects of warpage.