Silicon Carbide Wafer Surface Roughening Suppression
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Solution Overview
Problem
The existing methods for producing semiconductor devices using silicon carbide wafers face issues with surface roughening during heat treatment, which adversely affect the device's properties, despite attempts to suppress step bunching, such as those using a graphite cap, as surface roughening is not sufficiently mitigated.
Innovation Solution
The method involves heating the silicon carbide wafer in an atmosphere containing silicon carbide vapor generated from a source other than the wafer, using a sacrificially sublimable silicon carbide body to suppress sublimation and surface roughening, while maintaining conventional heat-treating equipment and conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heat treatment is performed at high temperature (not less than 1,600°C) to activate introduced impurities, then the activation of impurities is improved, but surface roughening occurs and macrosteps are formed by step bunching
Solution Approach 1:
A graphite cap is introduced as an intermediary layer between the silicon carbide wafer surface and the high-temperature environment. The graphite cap serves as a protective mediator that prevents direct interaction between the wafer surface and the harsh thermal conditions, thereby suppressing step bunching and surface roughening while allowing the underlying impurity activation process to proceed effectively.
Solution Approach 2:
The graphite cap is formed on the wafer surface before the heat treatment process begins. This preliminary protective action ensures that when the high-temperature treatment is subsequently applied, the surface is already protected against step bunching and roughening, allowing the impurity activation to occur without surface degradation.
2Ease of manufacture
If the wafer is heat-treated in conventional atmosphere, then the heat treatment process is simple, but the surface condition deteriorates due to sublimation and step bunching
Solution Approach 1:
The heat treatment is performed in a specially controlled inert atmosphere containing silicon-containing gases (such as silane). This modified inert atmosphere prevents the sublimation and step bunching that occur in conventional atmospheres, while still allowing the heat treatment process to proceed with minimal complexity addition. The atmosphere acts as a protective environment that maintains surface integrity during high-temperature processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses surface roughening and subsequent property degradation of semiconductor devices, even at high temperatures, by creating a controlled environment with a silicon carbide vapor atmosphere, enhancing the smoothness and performance of semiconductor devices like MOSFETs.
Implementation Method 1
the surface roughening occurs caused by the sublimation of silicon carbide. When the wafer is heat-treated in an atmosphere containing a vapor of silicon carbide, the sublimation of silicon carbide from the surface of the wafer is suppressed.
Data Source
AI summary
The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.