SiC Epitaxial Wafer Stress Profiling for Warp Suppression
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Solution Overview
Problem
SiC epitaxial wafers often warp due to the stacking of a SiC epitaxial layer, causing issues in photolithographic processing and positional accuracy during semiconductor processes, and existing methods to reduce stress do not sufficiently suppress this warpage.
Innovation Solution
Increase the tensile stress in the circumferential direction of the SiC substrate's outer periphery relative to the center, specifically by 10 MPa or more, to counteract warping by applying an outward force on the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a SiC epitaxial layer is stacked on a SiC substrate, then the functional properties of the semiconductor device are improved, but the SiC epitaxial wafer warps due to stress accumulation
Solution Approach 1:
The invention applies preliminary counter-stress to the SiC substrate before stacking the epitaxial layer. By increasing the tensile stress in the circumferential direction of the outer periphery region (within 10mm from the outer peripheral edge) to be higher than in the center region, the substrate is pre-conditioned to resist the compressive stress that will be generated when the epitaxial layer is stacked, thereby preventing warpage.
Solution Approach 2:
The invention creates a non-uniform stress distribution in the SiC substrate by locally increasing the tensile stress in the outer periphery region compared to the center region. This local stress enhancement in specific areas (within 10mm from the edge) provides targeted counteraction to the stress concentration that occurs at the edges during epitaxial layer stacking, effectively controlling warpage while maintaining overall substrate integrity.
2Stress or pressure
If methods to reduce stress are applied to the SiC substrate, then the stress level decreases, but the warpage of the SiC epitaxial wafer is not sufficiently suppressed
Solution Approach 1:
Rather than uniformly reducing stress across the entire substrate, the invention applies local stress enhancement in the outer periphery region (within 10mm from the edge). By making the tensile stress in this specific region higher than in the center, it creates a stress gradient that counteracts the warpage-inducing compressive stress during epitaxial layer stacking, achieving sufficient warpage suppression without overall stress reduction.
Solution Approach 2:
The invention applies preliminary counter-stress in the form of enhanced tensile stress in the outer periphery region before the epitaxial layer is stacked. This pre-applied stress acts in opposition to the compressive stress that will be generated during stacking, thereby preventing warpage before it occurs, rather than attempting to reduce stress after warpage has been induced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively suppresses warpage of the SiC epitaxial wafer to 50 μm or less, maintaining accuracy during transportation and focusing in fine lithography processes.
Implementation Method 1
the tensile stress of the first outer peripheral point in a circumferential direction of the first outer peripheral point is larger than the tensile stress of the first center point in the circumferential direction of the first outer peripheral point
Data Source
AI summary
A SiC epitaxial wafer including: a SiC substrate; and a SiC epitaxial layer stacked on one surface of the SiC substrate, wherein a diameter of the SiC substrate is 195 mm or more, and a warp is 50 μm or less.