SiC Power Switching Devices Wiring Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing paralleled SiC power switching devices face limitations due to unequal switching losses and transient current overshoots, restricting their maximum switching frequency and current capacity, and require additional auxiliary devices, increasing system complexity and cost.
Innovation Solution
The design method involves arranging multiple wiring separation slots on a PCB circuit board to increase parasitic inductance between adjacent power half-bridges, connecting DC capacitors in parallel, and using a laminated busbar wiring for the driving circuit to ensure uniform drive signals, thereby improving current sharing performance without additional auxiliary devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple SiC devices are connected in parallel to increase current capacity, then the current capacity increases, but unequal switching losses and transient current overshoots occur between devices
Solution Approach 1:
The patent divides the PCB layout into separate wiring separation slots for each power half-bridge, physically segmenting the current paths. This segmentation increases parasitic inductance between adjacent half-bridges, which isolates the transient current overshoots of each device and improves current sharing performance during parallel operation
Solution Approach 2:
The patent applies different wiring configurations to different parts of the circuit. Specifically, wiring separation slots are introduced between adjacent power half-bridges to increase parasitic inductance locally, while the driving circuit uses laminated busbar wiring to reduce loop parasitic inductance. This localized quality adjustment optimizes current sharing without compromising drive signal uniformity
2Reliability
If additional auxiliary devices such as power coupling inductors and high-bandwidth current sensors are added to improve current sharing, then current sharing performance improves, but system complexity and cost increase
Solution Approach 1:
The patent extracts the function of current sharing improvement from traditional auxiliary devices (power coupling inductors and high-bandwidth current sensors) and implements it through PCB wiring optimization. By taking out the need for these additional components and replacing them with wiring separation slots, the system achieves improved current sharing performance while reducing complexity and cost
Solution Approach 2:
The patent enables the PCB wiring structure itself to provide the current sharing function that traditionally required separate auxiliary devices. The wiring separation slots automatically create the necessary parasitic inductance to equalize transient currents, making the system self-regulating without external control or additional sensing components
3Reliability
If wiring separation slots are added to increase parasitic inductance between half-bridges, then transient current sharing improves, but PCB layout complexity increases
Solution Approach 1:
The patent merges the current sharing function with the existing PCB wiring structure. Instead of adding separate components or complex routing, the wiring separation slots are integrated directly into the PCB layout, combining structural support with electrical function. This merging approach improves transient current sharing while maintaining relatively simple PCB fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the transient current sharing performance of SiC devices, enabling their stable and reliable application in high-power and high-current converters, reducing system complexity and cost while maintaining optimal performance.
Implementation Method 1
at least three wiring separation slots are arranged in parallel and in sequence on a PCB circuit board; wherein a power half-bridge composed of two SiC devices is arranged in each wiring separation slot, thereby increasing a parasitic inductance between adjacent power half-bridges
Data Source
AI summary
The disclosure provides a design method for paralleled SiC power switching devices based on wiring optimization which belongs to the field of power electronics technology, aiming at the problem that in the existing scheme of paralleled SiC devices, the optimal performance of SiC devices cannot be presented with paralleled multiple SiC devices due to limitations of the unequal switching losses and transient currents. The design method comprises at least three wiring separation slots being arranged in parallel and in sequence on a PCB circuit board; wherein a power half-bridge composed of two SiC devices is arranged in each wiring separation slot, thereby increasing a parasitic inductance between adjacent power half-bridges. The disclosure can improve the current sharing performance of the switching transient current existing in the application of multiple paralleled SiC devices, so that SiC devices can be applied to high-power and high-current power electronic converters stably and reliably.