Silicon Carbonitride Interconnect Layer for Low RC Delay
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Solution Overview
Problem
As semiconductor feature sizes decrease, increasing parasitic capacitance leads to larger resistance-capacitance (RC) delay in integrated chips, which hinders performance improvement.
Innovation Solution
A semiconductor device with a low RC delay is manufactured using a single damascene process, incorporating a hermetic etch stop layer and inter-metal dielectric (IMD) layers made of low dielectric constant materials like silicon carbonitride, and using silicon carbonitride for liners and capping layers to reduce capacitance and prevent oxidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are decreased to improve integration density, then integration density is improved, but parasitic capacitance increases leading to larger RC delay
Solution Approach 1:
The patent changes the dielectric constant parameter of the inter-metal dielectric material from conventional values to low-k values (k<3.5), which directly reduces parasitic capacitance and RC delay while maintaining the reduced feature sizes required for high integration density
Solution Approach 2:
The patent uses composite material structures including low-k dielectric materials combined with specific liner materials (such as cobalt, ruthenium, or tungsten) and etch stop layers, creating a multi-layer composite structure that simultaneously achieves low capacitance, oxidation prevention, and manufacturing compatibility
2Reliability
If low-k dielectric materials are used to reduce parasitic capacitance, then RC delay is reduced, but oxidation of interconnect structures occurs
Solution Approach 1:
The patent introduces liner materials (such as cobalt, ruthenium, or tungsten) as intermediary layers between the low-k dielectric material and the interconnect structures, which serve as protective barriers preventing oxidation while maintaining the low capacitance properties of the low-k dielectric
Solution Approach 2:
The patent creates a composite structure where low-k dielectric materials are combined with oxidation-resistant liner materials, achieving both low RC delay and protection against oxidation through the synergistic properties of the composite system
3Ease of manufacture
If conventional damascene processes are used for manufacturing, then manufacturing process is simpler, but oxidation prevention and capacitance reduction are insufficient
Solution Approach 1:
The patent modifies the conventional damascene process parameters by incorporating low-k dielectric materials and specific liner materials, achieving both improved electrical performance (lower capacitance) and better oxidation resistance while maintaining process feasibility
Solution Approach 2:
The patent employs composite material systems in the damascene process, combining low-k dielectrics with specialized liners and etch stop layers, which simultaneously address capacitance reduction and oxidation prevention requirements within an manufacturable process framework
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces RC delay by minimizing capacitance and preventing oxidation, thereby enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
the resulting parasitic capacitance increases, leading to larger resistance-capacitance (RC) delay
Implementation Method 2
materials having low dielectric constant (k) values are used
Implementation Method 3
oxidation of the interconnect structures disposed below the etch stop layer
Data Source
AI summary
A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes a dielectric layer, an interconnect structure disposed in the dielectric layer, and an etch stop layer which is disposed on a lower end surface of the interconnect structure and which includes silicon carbonitride represented by a general formula of SixCyNz, wherein x is a silicon content ranging from 30 atomic % to 60 atomic %, y is a carbon content ranging from 25 atomic % to 60 atomic %, z is a nitrogen content ranging from 10 atomic % to 20 atomic %, and a sum of x, y, and z is 100 atomic %.