SiCN Interfacial Layer in 3D NAND for Data Retention
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Solution Overview
Problem
Three-dimensional vertical NAND devices face challenges in data retention due to shifts in device characteristics caused by electrical stress during write/erase cycles, leading to degradation of write/erase data retention, primarily attributed to layer mixing between silicon nitride and silicon oxide layers.
Innovation Solution
Incorporating a thin silicon carbon nitride (SiCN) film between the charge trapping layer and the tunneling dielectric layer interface to suppress mixing of silicon nitride and silicon oxide, thereby reducing degradation of write/erase data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride and silicon oxide layers are used in vertical NAND devices, then device functionality is achieved, but layer mixing occurs during write/erase cycles causing data retention degradation
Solution Approach 1:
A silicon carbon nitride (SiCN) interfacial layer is introduced between the silicon nitride charge trapping layer and the silicon oxide tunneling dielectric layer. This intermediary layer prevents direct contact and mixing between the silicon nitride and silicon oxide layers during electrical stress, thereby maintaining layer composition stability and improving data retention reliability.
2Productivity
If write/erase cycles are performed in vertical NAND devices, then data programming is achieved, but electrical stress causes layer mixing and characteristic shifts
Solution Approach 1:
The SiCN interfacial layer is deposited beforehand between the silicon nitride and silicon oxide layers to provide a protective barrier that cushions against the harmful effects of electrical stress during subsequent write/erase cycles. This pre-established protective layer prevents layer mixing and characteristic shifts that would otherwise occur during programming operations.
Data Source
AI summary
An alternating stack of insulating layers and spacer material layers is formed located over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory stack structure is formed within each memory opening. Each memory stack structure includes a memory film and a vertical semiconductor channel. A silicon nitride layer is formed over a sidewall of each memory opening as a component of the memory film. A silicon carbon nitride interfacial layer is formed on the silicon nitride layer, and a tunneling dielectric layer is formed on the silicon carbon nitride interfacial layer.