SiCr Thin Film Resistor Integration with TCR Offset
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Solution Overview
Problem
Current integrated circuit designs face challenges in integrating thin film resistors with various sheet resistances and temperature coefficients of resistance (TCRs) due to difficulties in controlling thermal cycles and compatibility with metallization layers, particularly for achieving precise zero or positive TCR values, especially for SiCr materials.
Innovation Solution
The integration of multiple thin film resistors with different sheet resistances and TCRs is achieved by forming oxide layers and metallization elements in a structured sequence, where one SiCr resistor is annealed to adjust its TCR before subsequent processing, and another SiCr resistor is deposited with precise TCR and sheet resistance values, using vanadium silicide layers for electrical connections, allowing for stable and adjustable resistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If thermal cycles are used to adjust TCR of thin film resistors, then TCR precision is improved, but subsequent processing compatibility deteriorates
Solution Approach 1:
The patent applies preliminary action by performing the thermal annealing process on the first SiCr resistor layer before depositing subsequent metallization layers and oxide layers. This sequence allows the TCR to be adjusted to the desired precision (including zero TCR) before any subsequent processing steps that might be incompatible with high-temperature thermal cycles. The preliminary annealing ensures that the resistor achieves its target electrical properties while avoiding conflicts with later fabrication steps.
2Adaptability or versatility
If multiple thin film resistor layers are integrated, then circuit functionality is improved, but thermal cycle control difficulty increases
Solution Approach 1:
The patent applies segmentation by dividing the resistor integration into separate layers (first SiCr resistor layer and second SiCr resistor layer) with distinct processing sequences. Each layer can be independently annealed and characterized, allowing different TCR values and sheet resistances to be achieved without requiring complex coordinated thermal cycling of multiple layers. This segmentation simplifies the overall thermal cycle control while enabling multiple resistor functions in a single integrated structure.
3Measurement precision
If high-precision zero TCR resistors are manufactured, then measurement accuracy is improved, but manufacturing feasibility deteriorates
Solution Approach 1:
The patent applies parameter changes by utilizing the relationship between annealing temperature, annealing time, and resulting TCR values. By carefully controlling these thermal parameters during the annealing process, the invention achieves precise zero TCR (or other target TCR values) in SiCr resistor layers. The empirical curves mentioned in the background provide a roadmap for selecting appropriate annealing parameters to achieve desired TCR precision, making the manufacturing of high-precision zero TCR resistors feasible through controlled parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of stable, high-precision thin film resistor structures that can offset TCRs of other circuit elements, providing accurate combinations of sheet resistances and TCRs, enhancing the precision and stability of integrated circuit components.
Implementation Method 1
The SiCr layer is annealed to adjust its TCR to a desired value
Implementation Method 2
providing electrical connection between metallization elements and circuit elements
Data Source
AI summary
An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a semiconductor substrate (1), a first thin film resistor (3) disposed on the first oxide layer (2), and a second oxide layer (14) disposed over the first oxide layer (2) and first thin film resistor (3). A second thin film resistor (15) is formed on the second oxide layer (14) and a third oxide layer (16) is formed over the second thin film resistor (15) and the second oxide layer (14). Interconnect metallization elements (12A,B &22A,B) disposed on at least one of the second (14) and third (16) oxide layers electrically contact the circuit element (4), terminals of the first thin film resistor (3), and terminals of the second thin film resistor (15), respectively, through corresponding contact openings through at least one of the second (14) and third (16) oxide layers.