Side Bottom Contact RRAM Structure for Planar Topography
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Solution Overview
Problem
As RRAM cells shrink in size, the conductive material often fails to properly fill the opening in the dielectric layer, resulting in depressions or voids on the bottom electrode, leading to non-planar topographies that negatively affect data storage and reliability.
Innovation Solution
An integrated circuit with a side bottom contact structure is used to connect the bottom electrode to the underlying metal line, providing a planar surface and eliminating the need for complex patterning processes by forming the contact structure alongside the electrode, rather than within an opening.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the RRAM cell size is reduced, then the integration density is improved, but the conductive material fails to properly fill the opening resulting in depressions or voids on the bottom electrode
Solution Approach 1:
The patent transitions from a vertical bottom-contact structure (where the conductive via is directly beneath the electrode) to a side-contact structure (where the conductive via is positioned laterally adjacent to the electrode). This dimensional reconfiguration eliminates the need for deep vertical vias that are difficult to fill at scaled dimensions, thereby resolving the filling failure issue while maintaining electrical connectivity.
Solution Approach 2:
Instead of forming the conductive via first and then placing the electrode on top (conventional approach), the patent inverts the sequence by forming the electrode structure first and then creating the side-attached conductive via. This inversion allows the via to be formed in a more accessible lateral position rather than requiring precise vertical alignment and complete filling of a deep opening.
2Productivity
If the opening in the dielectric layer is reduced to shrink cell size, then the integration density is improved, but the conductive material fails to properly fill the opening leading to non-planar topographies
Solution Approach 1:
The patent moves the conductive connection from a vertical dimension (deep via beneath the electrode) to a lateral dimension (side-attached via). This dimensional shift transforms the geometry from a high aspect-ratio vertical hole that is difficult to fill planarly to a lateral connection that naturally maintains a planar surface on the electrode.
3Ease of manufacture
If the conventional bottom contact structure is used, then the manufacturing process is simpler, but the non-planar topography negatively affects data storage and reliability
Solution Approach 1:
The patent resolves the reliability issue by reconfiguring the contact geometry from vertical to lateral. This side-contact architecture inherently produces planar electrode surfaces that improve data storage reliability, while the overall manufacturing process remains compatible with existing semiconductor fabrication techniques.
Data Source
AI summary
The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.