Side-by-Side IC Package Structure for Thermal and Warpage Control
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Solution Overview
Problem
Existing integrated circuit package structures fail to fully address the requirements of lower heights, smaller sizes, and cost reductions in modern mobile electronic devices, as they limit bus speed and introduce thermal dissipation and package warpage issues.
Innovation Solution
The integrated circuit package structure incorporates a side-by-package-on-package configuration with conductive lines formed in the package substrate, allowing for improved electrical connectivity and thermal dissipation by positioning semiconductor chips with different functionalities and encapsulant layers to enhance operation efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integrated circuits are stacked into a single package using conventional PIP technology, then more functions are integrated, but the package height and size reduction requirements are not fully met
Solution Approach 1:
The patent transitions from conventional vertical stacking (single dimension) to a side-by-side configuration with conductive lines extending laterally (adding horizontal dimension). Multiple semiconductor chips are arranged adjacent to each other on the same substrate plane, with bus lines routing through the substrate to connect chips laterally rather than vertically, thereby reducing package height while maintaining function integration.
Solution Approach 2:
The package is segmented into multiple independent chip modules arranged side-by-side rather than stacked. Each chip maintains its own functional unit with dedicated connection pathways through the substrate, allowing parallel arrangement that reduces vertical height while preserving individual chip functionalities and their interconnections.
2Productivity
If more integrated circuits are packed into smaller physical space, then device density increases, but thermal dissipation becomes problematic
Solution Approach 1:
The substrate is designed with localized thermal management features including thermal vias and heat dissipation pathways positioned beneath or adjacent to high-power chip regions. The side-by-side arrangement creates spatial separation between heat-generating chips, allowing localized cooling strategies to be applied to specific hot spots rather than requiring uniform thermal management across a compact stacked structure.
Solution Approach 2:
Heat is extracted laterally through the substrate rather than being trapped vertically between stacked chips. The substrate acts as a heat spreader with thermal pathways extending horizontally to dissipate heat from multiple chips simultaneously, preventing thermal accumulation that would occur in tightly stacked configurations.
3Volume of moving object
If conventional PIP structures are used to reduce package size, then more circuits fit in less space, but bus speed limitations are introduced
Solution Approach 1:
Data transmission shifts from vertical pathways through stacked chips to lateral pathways through the substrate. The side-by-side chip arrangement with horizontal bus lines routing through the substrate enables shorter and more direct signal paths between adjacent chips, improving bus speed while maintaining compact package dimensions.
4Volume of moving object
If integrated circuits are densely packed to reduce size, then physical space is optimized, but package warpage issues increase
Solution Approach 1:
The package structure is segmented into multiple independent chip-substrate units arranged side-by-side rather than stacked. This segmentation distributes mechanical stress across separate regions, preventing the cumulative warpage effects that occur when multiple chips are tightly stacked and thermally cycled, thereby improving overall package stability.
Data Source
AI summary
An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having opposite first and second surfaces, wherein a first semiconductor chip is disposed over a first portion of the first surface of the first package substrate. In addition, a second integrated circuit (IC) package is disposed on a second portion different from the first portion of the first surface of the first package substrate, including: a second package substrate, having opposite third and fourth surfaces, wherein a second semiconductor chip is disposed over a portion of the third surface of the second package substrate, and the second semiconductor chip has a function different from that of the first semiconductor chip.