Side-by-Side IC Substrate Layout With 3D Interconnect Routing
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Solution Overview
Problem
The increasing complexity of integrated circuit (IC) devices leads to a higher need for heat dissipation and device-to-device interconnects, which often results in increased costs, reduced performance, and larger IC package sizes.
Innovation Solution
A substrate with a first layer stack and a second layer stack is used, where the first layer stack includes multiple metal layers interspersed with dielectric layers, and the second layer stack defines a plateau relative to the first layer stack, allowing for efficient routing of conductive paths between IC devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more interconnect layers are used to support increased number of devices, then device interconnection capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent introduces a second layer stack disposed at a different elevation than the first layer stack, creating a three-dimensional interconnection architecture. This vertical dimensionality allows traces to be routed on one layer stack while via pads connect to contacts on the other layer stack, enabling device interconnection without requiring additional interconnect layers within the same plane, thus reducing manufacturing complexity while maintaining interconnection capability.
2Adaptability or versatility
If more interconnect layers are used to support increased number of devices, then device interconnection capability is improved, but cost increases
Solution Approach 1:
By utilizing a second layer stack at a different elevation with contacts that can be directly connected to via pads on the first layer stack, the patent reduces the need for additional interconnect layers. This dimensional approach simplifies the manufacturing process and reduces costs associated with creating and managing multiple interconnect layers while still achieving the required device interconnection capability.
3Ease of manufacture
If traditional routing methods are used between devices, then manufacturing process is simple, but trace lengths are long and signaling performance is reduced
Solution Approach 1:
The patent enables shorter trace routing by allowing traces on the first layer stack to connect directly to contacts on the second layer stack through via pads, eliminating the need for traces to extend across the entire substrate area. This vertical connection approach maintains manufacturing simplicity while significantly reducing trace lengths and improving signaling performance.
4Area of stationary object
If devices are placed closer together to reduce package size, then form factor is improved, but heat dissipation and interconnect density challenges increase
Solution Approach 1:
The patent's two-layer stack architecture with vertical via pad connections enables devices to be placed closer together by providing efficient short-path interconnections. This reduces the horizontal distance signals must travel, allowing tighter device packing that reduces overall package size while the vertical connection paths help manage heat dissipation by reducing the thermal path length and improving thermal management efficiency.
Data Source
AI summary
A device includes a substrate that includes a first layer stack including multiple metal layers and multiple dielectric layers. A first metal layer includes contacts disposed in a first region and configured to electrically connect to a first IC device, via pads disposed in a second region, and traces electrically connected to the first contacts and to the via pads. One or more of the traces extend between a pair of the via pads. The substrate also includes a second layer stack disposed on the second region of the first metal layer. The second layer stack includes a dielectric layer and a second metal layer on the dielectric layer. The second metal layer defines second contacts configured to electrically connect to one or more second IC devices. The second layer stack also includes conductive vias extending between the via pads and the second contacts.