Side Channel Resistant Memory Operations via Random Access

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Solution Overview

Problem

Existing memory operations, such as memcpy, memcmp, and memset, are vulnerable to power analysis attacks and leak information that can be used by hackers to reconstruct sensitive data.

Innovation Solution

A method that involves accessing a buffer of bits, generating a random sequence of values, and using these values to determine the order in which to access the bits, thereby performing memory operations in a way that obfuscates the power or timing profile.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory operations are performed in a deterministic order (traditional memcpy, memcmp, memset), then processing efficiency is maintained, but power consumption patterns leak sensitive information

Engineering Contradiction:
Improvesecurity against power analysis attacksVSAvoidcomplexity of memory access pattern
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the memory access pattern variable and adaptive rather than fixed. A random permutation generator creates different access orders for each execution, and the system dynamically selects which memory locations to access based on this random permutation. This dynamic behavior ensures that power consumption patterns vary between executions, preventing attackers from deriving meaningful information through repeated power analysis attacks.

Inventive Principle:
Principle #15Dynamics

2Reliability

If random access patterns are used to thwart power analysis attacks, then security is improved, but processing time increases

Engineering Contradiction:
Improvesecurity against power analysis attacksVSAvoidprocessing time for memory operations
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-generating a random permutation of memory location indices before the actual memory operation begins. This random permutation is created once and then used to guide all subsequent memory accesses. By preparing the access pattern in advance rather than making random decisions during each memory access, the system minimizes overhead while maintaining security. The preliminary random permutation ensures that the same memory operation will have different access patterns across different executions, thwarting power analysis without significant time penalty.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If traditional memory operations are used, then platform compatibility is maintained, but vulnerability to power analysis attacks persists

Engineering Contradiction:
Improveplatform independenceVSAvoidsusceptibility to power analysis attacks
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies universality by designing a memory operation system that can function across different platforms while incorporating security features. The random permutation generator and the modified memory operation interface are implemented in a way that is platform-independent, using standard programming constructs and memory access mechanisms. This allows the same secure memory operation code to run on various hardware architectures and operating systems, providing both broad compatibility and protection against power analysis attacks simultaneously.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250131107A1Side channel resistant memory operations
Publication Date: 2025.04.24 GOOGLE LLC
  • US20250131107A1 patent drawing
  • US20250131107A1 patent drawing
  • US20250131107A1 patent drawing

AI summary

Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for privacy preserving digital component provider. In some implementations, a method includes accessing a buffer including one or more sets of bits; generating a random sequence of values; generating, from the random sequence of values, a sequence of indices representing an order in which to access particular sets of bits of the buffer; in response to determining an index of the sequence of indices corresponds to a location in the buffer, accessing a set of the particular sets of bits of the buffer at the index in the order of the sequence of indices; and performing one or more memory operations on the set of the one or more sets of bits after accessing the set.