HBM Side-Edge Interconnection Without TSVs for Lower Chip Heat
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 2.5D/3D ICs face challenges in power, performance, area, and cost optimization due to bottom/top electrical interconnects, and insufficient heat dissipation from stacked DRAM memory semiconductor dies, leading to elevated chip temperatures.
Innovation Solution
A memory stack design with horizontally separated semiconductor dies and edge pads, utilizing high thermal conductivity layers between and around dies, eliminating the need for through-silicon vias and interposers, and incorporating a logic die with memory controller and processor circuit without an interposer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) and interposers are used in 2.5D/3D ICs for electrical interconnection, then electrical connectivity between stacked dies is achieved, but manufacturing complexity and alignment difficulty increase severely
Solution Approach 1:
The patent extracts and eliminates the TSV and interposer components from the 3D IC structure. Instead of using through-silicon vias and separate interposer substrates for electrical interconnection, the invention directly bonds semiconductor dies to the packaging substrate through edge pads, removing the complex TSV formation and alignment processes while maintaining electrical connectivity functionality
Solution Approach 2:
The patent inverts the traditional interconnection approach by moving electrical pads from the top/bottom surfaces to the side edges of the semiconductor dies. This edge pad configuration allows direct electrical connection to the packaging substrate without requiring vertical TSV penetrations, fundamentally changing the interconnection topology to simplify manufacturing
2Quantity of substance
If multiple DRAM memory semiconductor dies are stacked vertically in 2.5D/3D ICs to increase memory capacity, then integration density is improved, but heat dissipation capability deteriorates and chip temperature increases
Solution Approach 1:
The patent transitions from vertical stacking to horizontal arrangement of semiconductor dies. By positioning dies side-by-side on the packaging substrate and utilizing edge pads for interconnection, the invention creates a two-dimensional memory array configuration that improves thermal access to each die individually, preventing heat accumulation that occurs in tightly stacked vertical configurations
Solution Approach 2:
The patent segments the memory structure into multiple independently connected semiconductor dies arranged horizontally rather than stacked vertically. Each die is separately bonded to the packaging substrate with its own edge pads, creating discrete thermal zones that can be managed independently, thereby improving overall heat dissipation capability while maintaining high memory capacity
3Reliability
If bottom/top electrical interconnects are used in 2.5D/3D ICs, then electrical connection between stacked components is achieved, but optimization of power, performance, area and cost (PPAC) is severely constrained
Solution Approach 1:
The patent introduces dynamic flexibility in the interconnection scheme by using edge pads that can be configured in various patterns and connected to different locations on the packaging substrate. This enables designers to optimize PPAC parameters by selecting different pad arrangements and connection topologies, providing adaptability that fixed bottom/top interconnect structures cannot offer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances heat dissipation and reduces chip temperature, optimizing power and performance while maintaining a compact design, thus addressing the limitations of traditional 2.5D/3D ICs.
Implementation Method 1
utilizing high thermal conductivity layers between and around dies
Data Source
AI summary
An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall. The IC structure further includes a logic die with memory controller and processor circuit under the memory stack and electrically connected to the plurality of edge pads of each semiconductor memory die, and a packaging substrate under and electrically connected to the logic die with memory controller and processor. There is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die.