Top-and-Side Gate Overlap for High-Speed Semiconductor Devices
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Solution Overview
Problem
Semiconductor display devices require high-speed operation and high stress resistance, particularly in flexible substrates, to support increased pixel density and narrow bezel designs.
Innovation Solution
A semiconductor device structure featuring a semiconductor film with a channel formation region and impurity regions, covered by insulating films and gate electrodes, with source and drain electrodes connected to both side and top portions, enhancing carrier flow and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If driver circuits operate at higher speeds to support increased pixel density, then image quality and resolution improve, but stress resistance of the device deteriorates
Solution Approach 1:
The patent applies dimensionality change by forming the gate electrode not only over the channel formation region but also extending to overlap with the impurity regions. This three-dimensional extension of the gate electrode structure enables simultaneous control of carrier flow in the channel while providing stress compensation in the impurity regions, resolving the contradiction between high-speed operation and stress resistance
Solution Approach 2:
The patent uses composite material structures by combining the gate electrode with stress compensation layers and insulating films in a multi-layer configuration. This composite structure provides both the electrical control needed for high-speed operation and the mechanical support needed for stress resistance, allowing the device to achieve both objectives simultaneously
2Ease of manufacture
If source and drain electrodes contact only top portions of semiconductor film, then manufacturing is simpler, but contact resistance increases
Solution Approach 1:
The patent applies dimensionality change by extending source and drain electrodes to contact both the top surface and side surfaces of the semiconductor film in the impurity regions. This multi-point contact configuration reduces contact resistance by providing multiple conduction paths while remaining compatible with standard thin-film fabrication processes
Solution Approach 2:
The patent merges the contact function into a unified structure where source and drain electrodes simultaneously contact the semiconductor film at multiple locations (top and sides), combining multiple contact points into a single integrated electrode structure that reduces contact resistance without complicating manufacturing
3Adaptability or versatility
If flexible substrate is used to widen application range, then adaptability improves, but stress resistance requirements increase
Solution Approach 1:
The patent applies preliminary anti-action by incorporating stress compensation structures in advance within the device architecture before stress damage can occur. The gate electrode extension and insulating film configuration are designed preemptively to counteract the stress generated by flexible substrate bending, preventing degradation before it happens
Solution Approach 2:
The patent changes material parameters by selecting specific materials for the gate electrode, insulating films, and semiconductor layers that have appropriate mechanical properties for flexible substrates. By optimizing the material composition and thickness parameters, the device achieves both flexibility compatibility and stress resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure enables high-speed operation and increased strength against stress, improving on-state current and field-effect mobility while supporting flexible substrates.
Implementation Method 1
a gate electrode overlapping the side and top portions of the semiconductor film in the channel formation region with the insulating film positioned between the gate electrode and the side and top portions
Implementation Method 2
an insulating film covering side and top portions of the semiconductor film in the channel formation region
Data Source
AI summary
A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.