Side I/O Chip Package and Cooling Assembly for High I/O Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Future generations of silicon chip manufacturing technology will drive higher performance semiconductor chips with increased transistor packing densities, leading to higher heat dissipation and increased I/O counts, which poses packaging challenges due to the risk of 'pop out' or 'pop off' issues with existing I/O configurations.
Innovation Solution
The solution involves relocating additional I/Os from the underside to the side of the chip package, utilizing passageways and mechanical features to guide cable connectors to side I/Os, which are integrated into the chip carrier and substrate, ensuring secure and efficient electrical connections while managing increased I/O counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional I/Os are added to accommodate increased transistor packing densities, then the I/O count is improved, but the risk of pop out or pop off issues increases
Solution Approach 1:
The patent relocates I/O connections from the traditional underside (single plane) to the side of the chip package, utilizing a different spatial dimension. This dimensional change allows I/Os to be distributed along the side surface, reducing concentration of loading forces at any single location and thereby mitigating pop out or pop off risks while accommodating increased I/O counts
2Reliability
If I/Os are relocated to the side of the chip package, then the pop out and pop off effects are limited, but the device complexity increases
Solution Approach 1:
The patent integrates the side I/O structure with the cooling assembly, where the cooling assembly incorporates passageways and mechanical features that guide cable connectors to side I/Os. This merging of functions reduces overall system complexity by combining multiple components into a unified structure rather than adding separate systems
3Stability of the object's composition
If loading forces are distributed more evenly, then the integrity of the chip package assembly is maintained, but the structural complexity increases
Solution Approach 1:
The cooling assembly serves multiple functions: it provides thermal management, incorporates passageways for cable routing, includes mechanical features for guiding connectors, and distributes loading forces. This multi-functionality reduces the need for separate structural components, thereby maintaining assembly integrity without proportionally increasing complexity
Data Source
AI summary
A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.