Side Junction Formation in Semiconductor Devices
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Solution Overview
Problem
Current methods for fabricating semiconductor devices with vertical gate structures face challenges in forming stable side junction regions, which affect the electrical isolation and threshold voltage of the devices.
Innovation Solution
A method involving etching a substrate to form trenches, creating a junction region, and forming a bit line connected to the side junction through a series of etching and annealing processes, including the use of doped layers and liner layers to achieve a stable side junction region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional OSC process with ion-implantation is used to form side junction region, then junction region can be formed, but the structure is complex and threshold voltage reduction occurs
Solution Approach 1:
The patent extracts the dopant source from the complex ion-implantation process and places it directly into the trench as a doped layer. This eliminates the need for separate ion-implantation equipment and process steps, simplifying the fabrication process while maintaining side junction formation capability.
Solution Approach 2:
The dopant is pre-loaded into the trench as a doped layer before the annealing process. This preliminary action ensures that the dopant is already in position to form the side junction region, eliminating the need for subsequent ion-implantation steps and preventing threshold voltage reduction.
2Manufacturing precision
If multiple process steps (ion-implantation, annealing, masking) are used to form side junction, then junction region can be formed, but manufacturing cost and time increase
Solution Approach 1:
The patent merges the dopant deposition and side junction formation into a single annealing process. The doped layer in the trench serves as both the dopant source and the structure that will become the side junction, eliminating the need for separate ion-implantation and masking steps.
Solution Approach 2:
The dopant is pre-positioned in the trench as a doped layer before annealing. This preliminary placement eliminates the need for time-consuming ion-implantation and masking steps during the actual junction formation process, significantly improving fabrication efficiency.
3Ease of manufacture
If doped layer is formed in trench to simplify process, then fabrication is simplified, but dopant control precision may be compromised
Solution Approach 1:
The patent controls dopant concentration by adjusting the annealing process parameters (temperature, time, atmosphere) rather than relying on ion-implantation dosage control. The doped layer's dopant concentration and depth are precisely controlled through these thermal parameters, maintaining manufacturing precision while simplifying the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the fabrication process, reduces development costs, and enhances the off-state characteristics of semiconductor devices by forming a stable body-tied structure and suppressing the threshold voltage reduction phenomenon.
Implementation Method 1
etching a substrate to form a trench
Implementation Method 2
a dopant is ion-implanted into the portion of the one sidewall of the active region to form the side junction region
Implementation Method 3
an annealing process may be performed to form the side junction region
Data Source
AI summary
A method for fabricating a semiconductor device, including etching a substrate to form a trench, forming a junction region in the substrate under the trench, etching the bottom of the trench to a certain depth to form a side junction, and forming a bit line coupled to the side junction.