Semiconductor Package Side-Rail Structure for Thin Substrate Warpage
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Solution Overview
Problem
The semiconductor industry faces challenges with warpage in thin semiconductor substrates, leading to low yield rates during manufacturing due to handling difficulties, which is a critical issue in weight reduction and miniaturization efforts.
Innovation Solution
A substrate structure with a specific design including a chip attach area, upper and lower side rails, and stress relief and reinforcing structures is used, where the stress relieving ability and structural strength are strategically distributed to reduce warpage, and an encapsulant is formed to cover the semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If weight reduction and miniaturization techniques are used, then the semiconductor substrate becomes thinner and lighter, but the substrate becomes difficult to handle due to large warpage
Solution Approach 1:
The patent applies local quality by creating non-uniform stress distribution through selectively removing material only from specific regions (first and second regions) while leaving other regions intact. This localized material removal allows the substrate to maintain structural integrity in critical areas while reducing overall weight and inducing controlled stress relief to minimize warpage, thereby improving handling ease without compromising substrate strength
2Weight of moving object
If weight reduction and miniaturization techniques are used, then the semiconductor substrate becomes thinner and lighter, but the yield rate decreases due to manufacturing problems
Solution Approach 1:
The patent improves yield rate by applying local quality through selective material removal from specific regions. This localized approach reduces warpage and manufacturing defects in critical areas while maintaining overall substrate integrity, leading to higher successful production rates without requiring complete redesign of the entire substrate structure
Solution Approach 2:
The patent applies segmentation by dividing the substrate into distinct regions (first region, second region, and other regions) with different material densities. This regional segmentation allows independent optimization of each zone - removing material from first and second regions to reduce stress concentration points that cause warpage, while preserving material in other regions for structural support, thereby improving overall manufacturing yield
3Weight of moving object
If material is removed from the substrate to reduce weight, then the substrate weight decreases, but the structural strength may be compromised
Solution Approach 1:
The patent resolves the strength-weight contradiction by applying local quality through selective material removal. By removing material only from first and second regions while preserving material in other regions, the substrate achieves weight reduction without compromising overall structural strength. The remaining material in preserved regions provides necessary structural support, while the removed regions reduce stress concentration and overall weight
Solution Approach 2:
The patent uses segmentation to divide the substrate into functional zones with different material densities. First and second regions have reduced material density for weight reduction and stress relief, while other regions maintain full material density for structural strength. This segmented approach allows the substrate to achieve optimal strength-to-weight ratio by assigning different material properties to different functional areas
Data Source
AI summary
A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.