Semiconductor Package Side-Surface Interconnect for Lower-Chip Cooling
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Solution Overview
Problem
The existing package-on-package semiconductor structure faces limitations in heat dissipation due to the presence of the upper package, which restricts the thickness of the lower package's semiconductor chip and increases the turn-around time and number of process steps.
Innovation Solution
The proposed semiconductor package design includes a first semiconductor package with a redistribution layer, a substrate with wiring layers, and a semiconductor chip, along with a second semiconductor package stacked on top. This design allows for improved heat dissipation by optimizing the placement of the second semiconductor package above the substrate, eliminating the need for a backside redistribution layer or interposer substrate, and reducing the overlap with the first semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a backside redistribution layer or interposer substrate is introduced for electrical connection, then electrical connection between packages is achieved, but the turn-around time and number of process steps increase
Solution Approach 1:
The patent extracts and eliminates the backside redistribution layer or interposer substrate from the package structure. Instead of adding these intermediate components, the invention uses the side surface of the substrate as the direct connection interface, removing unnecessary elements to reduce process complexity and turn-around time while maintaining electrical connection functionality
Solution Approach 2:
The patent transitions from a conventional planar connection approach to a three-dimensional side-surface connection approach. By utilizing the side surface of the substrate rather than the top or bottom surface, the invention creates a new spatial dimension for electrical connection that eliminates the need for backside redistribution layers or interposer substrates
2Reliability
If a backside redistribution layer or interposer substrate is introduced, then electrical connection is achieved, but the number of process steps increases
Solution Approach 1:
The patent removes the backside redistribution layer or interposer substrate from the device structure, eliminating the additional fabrication processes required to create and integrate these components. The side-surface connection approach reduces device complexity by using existing substrate structures rather than adding new layers
3Temperature
If the thickness of the semiconductor chip is increased to improve heat dissipation, then heat dissipation performance improves, but space for the backside redistribution layer is compromised
Solution Approach 1:
By removing the backside redistribution layer requirement, the patent frees up vertical space that can be allocated to increasing semiconductor chip thickness for improved heat dissipation. The side-surface connection approach eliminates the space conflict between chip thickness and redistribution layer accommodation
Solution Approach 2:
The patent resolves the space conflict by moving the electrical connection interface to the side surface of the substrate, creating independent spatial zones. This allows the top surface area to be fully utilized for thicker semiconductor chips with enhanced heat dissipation capabilities without compromising connection functionality
Data Source
AI summary
A semiconductor package including a first semiconductor package that includes a redistribution layer, a substrate disposed on the redistribution layer and including a plurality of wiring layers, a first semiconductor chip disposed on the redistribution layer, and an encapsulant covering at least a portion of each of the substrate and the first semiconductor chip; and a second semiconductor package that is disposed on the first semiconductor package and includes a second semiconductor chip. The first semiconductor package includes a first side surface and a second side surface facing the first side surface. The plurality of wiring layers are disposed adjacent to the first side surface, the first semiconductor chip is disposed between the plurality of wiring layers and the second side surface, and a distance between the first semiconductor chip and the first side surface is greater than a distance between the first semiconductor chip and the second side surface.