Metallic Side-Wall Package Layout for High-Voltage Die Reliability
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Solution Overview
Problem
High voltage semiconductor device packaging faces challenges such as copper migration, oxidation of metallization, chemical degradation of encapsulation materials, and humidity sensitivity, leading to potential delamination and reliability issues under high electric fields.
Innovation Solution
A semiconductor device package design featuring a printed circuit board with metallic side walls and via bars of specific thicknesses, electrically connected to contact pads on the semiconductor die, and encapsulated in a polymer layer to address the challenges of high voltage and electric field interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedding technology is used for high voltage semiconductor devices, then device integration is achieved, but copper migration and oxidation of metallization occur due to high electric fields
Solution Approach 1:
The patent introduces an intermediate metallic layer (such as nickel or palladium) between the copper metallization and the embedding material. This intermediate layer acts as a barrier that prevents direct interaction between the high electric field and the copper, thereby preventing copper migration and oxidation while still allowing the embedding technology to be used for device integration.
Solution Approach 2:
The patent employs composite material structures combining multiple metallic layers with different properties. The stack includes copper for electrical conductivity, intermediate barrier layers for protection against migration and oxidation, and embedding materials for mechanical support. This composite structure resolves the contradiction by combining the benefits of embedding technology while protecting against its harmful effects.
2Object-affected harmful factors
If encapsulation material is used to protect the semiconductor die, then mechanical protection is provided, but chemical degradation and voltage drift occur due to interaction with high voltage electric fields
Solution Approach 1:
The patent introduces an intermediate metallic barrier layer between the encapsulation material and the semiconductor die metallization. This barrier layer prevents direct chemical interaction between the encapsulation material and the high voltage electric field, thereby preventing chemical degradation and voltage drift while maintaining the mechanical protection function of the encapsulation material.
Solution Approach 2:
The patent creates a chemically inert environment by using stable metallic barrier layers that do not react with the encapsulation material or decompose under high voltage conditions. These barrier layers effectively create a protected zone that isolates the sensitive semiconductor components from harmful chemical interactions.
3Ease of operation
If vias are used to connect the die metallization to outer layers, then electrical connection is established, but cracks occur at the via-to-die metallization interface
Solution Approach 1:
The patent employs composite material structures at the via interfaces, combining multiple metallic layers with different mechanical and electrical properties. This multi-layer composite structure distributes mechanical stresses and improves adhesion, preventing cracks from forming at the via-to-die metallization interface while maintaining electrical connectivity.
4Stability of the object's composition
If leadframe cavities are used to prevent delamination, then layer adhesion is improved, but manufacturing complexity increases due to dedicated cavity requirements for each die
Solution Approach 1:
The patent introduces a universal barrier layer structure that serves multiple functions simultaneously: it prevents copper migration, protects against oxidation, and provides adhesion promotion across all die locations. This universal approach eliminates the need for individualized leadframe cavities for each die, reducing manufacturing complexity while maintaining layer adhesion stability.
Data Source
AI summary
A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.