Sideband Bus Addressing for Memory Device Management
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Solution Overview
Problem
Conventional sideband bus technology is limited in addressing more than eight memory devices, requiring grouping and unique selection, which complicates configuration and access, especially at higher speeds where in-band signaling is necessary.
Innovation Solution
The proposed solution involves enumerating unique sideband addresses for each DRAM and DB device, allowing bi-directional communication through the sideband bus, and using strap pins with resistance values to set column addresses, enabling access to individual devices without relying on DDR CS signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional sideband bus technology is used to address memory devices, then the bus can be implemented with lower bandwidth interfaces (such as I2C/I3C), but the system is limited to addressing only eight memory devices requiring complex grouping and selection mechanisms
Solution Approach 1:
The patent extends the addressing capability from 8 devices to 16 devices by utilizing an additional address bit dimension. The sideband bus address space is expanded from 3 bits to 4 bits, allowing unique identification of each memory device without requiring grouping or selection mechanisms, thus resolving the contradiction between addressable device count and system complexity
Solution Approach 2:
The sideband bus is enhanced to serve multiple functions: it maintains its original low-bandwidth management capabilities while simultaneously providing extended addressing for up to 16 memory devices. This multi-functional approach allows the same bus interface to handle both device selection and extended addressing without requiring separate signaling paths
2Speed
If in-band signaling is used to access individual memory devices at higher speeds, then access speed improves, but the complexity increases and requires DDR CS signals
Solution Approach 1:
The patent introduces an intermediary addressing mechanism where the sideband bus provides a simplified path to individual memory devices through extended addressing, avoiding the need for complex in-band signaling sequences. The sideband address acts as a mediator that directly identifies the target device, eliminating the need for DDR CS signal coordination while maintaining access speed
Solution Approach 2:
The patent extracts the addressing function from the in-band signaling path and places it in the sideband bus. By taking out the device selection functionality and implementing it through extended sideband addressing, the system achieves fast access without requiring the full complexity of in-band signaling mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the management of more than eight DRAM and DB devices on a sideband bus, providing efficient configuration and access without the need for in-band signaling, thus overcoming the limitations of conventional sideband bus technology.
Implementation Method 1
using strap pins with resistance values to set column addresses
Data Source
AI summary
An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to enumerate respective sideband addresses to ten or more memory devices, and provide bi-directional communication with an individual memory device of the ten or more memory devices with a particular sideband address enumerated to the individual memory device. Other embodiments are disclosed and claimed.