Sideband Connectors for Parallel Debug Data Collection
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Solution Overview
Problem
Conventional electronic testing methods require disconnecting devices under test (DUTs) from the testing environment to connect external monitors for debugging, which is time-consuming and inefficient, especially when testing multiple DUTs in parallel, and often prevents testing in controlled conditions like temperature chambers.
Innovation Solution
A tester system with programmable accelerator circuits and load boards that allow for parallel collection of sideband information, including debug data, directly from DUTs within the test environment without external wiring, using sideband connectors that receive test-related information coincident with output signals, enabling efficient and effective debugging and data collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If external monitors are connected to DUTs for debugging, then debug information can be collected, but the DUTs must be disconnected from the testing environment and testing time is lost
Solution Approach 1:
The patent combines the debug monitoring function with the existing test environment by integrating sideband connectors into the load board architecture. This allows debug information to be captured through the same physical interface used for testing, eliminating the need for separate external monitoring equipment and the time-consuming disconnection/reconnection process.
Solution Approach 2:
The sideband connectors act as intermediaries that capture debug information directly from the DUT's output signals during normal testing operations. This intermediary mechanism allows simultaneous testing and debugging without requiring physical disconnection or external wiring harnesses.
2Productivity
If DUTs are tested in parallel, then throughput is improved, but individual debugging of problem DUTs becomes difficult
Solution Approach 1:
The load board is segmented into multiple independent sideband connector channels, each capable of capturing debug information from individual DUTs simultaneously. This segmentation allows parallel testing of multiple devices while maintaining the ability to isolate and debug any single problem DUT through its dedicated sideband connection.
Solution Approach 2:
The sideband connector architecture provides universal debugging capability across all parallel test channels. Each connector can independently capture debug information from any DUT, allowing the same debugging mechanism to serve multiple functions and multiple devices simultaneously without requiring specialized equipment for each DUT.
3Loss of information
If external wiring harnesses are used for debugging, then debug information can be obtained, but the DUT cannot remain in the testing environment
Solution Approach 1:
The debugging function is merged into the existing test environment architecture through integrated sideband connectors on the load board. This eliminates the need for external wiring harnesses and allows the DUT to remain in the controlled testing environment (such as temperature chambers) while debug information is captured through the same interface used for normal testing operations.
4Loss of information
If individual DUTs are debugged sequentially, then detailed debug information can be collected, but testing efficiency is reduced
Solution Approach 1:
The sideband connector system is segmented into multiple independent channels that can simultaneously capture debug information from multiple DUTs. This allows the testing system to maintain complete debug information collection capability while operating in parallel mode, thereby improving testing efficiency without sacrificing diagnostic completeness.
Data Source
AI summary
The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.