Sideband Interface Using CQEs for Network Packet Offload
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Solution Overview
Problem
As packet rates scale faster than silicon speed, incorporating a dedicated processor for computation-based tasks in network devices becomes increasingly challenging, leading to inefficiencies in handling auxiliary flows such as acknowledgments, telemetry, and congestion control.
Innovation Solution
Implement a hardware-implemented packet processing pipeline with multiple stages that trigger a sideband processor via Completion Queue Elements (CQEs) for executing tasks like congestion detection, acknowledgement processing, and telemetry, minimizing overhead by reusing CQE formats for both completion indications and task execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated processor is incorporated into the main pipeline for performing computation-based tasks, then task execution capability is improved, but device complexity and bandwidth consumption increase
Solution Approach 1:
The patent divides packet processing into two separate flows: a main flow handled by hardware pipeline stages and an auxiliary flow handled by a sideband processor. This segmentation allows computation-based tasks to be offloaded to a dedicated processor without complicating the main packet processing pipeline, thus improving task execution capability while maintaining manageable device complexity.
Solution Approach 2:
The patent introduces a sideband processor as an intermediary component that bridges the main packet processing pipeline and computation-based tasks. The sideband processor receives triggers from pipeline stages via completion queue elements and executes auxiliary tasks independently, enabling task execution without directly increasing main pipeline complexity.
2Productivity
If a dedicated processor is incorporated for computation-based tasks, then processing capability is improved, but bandwidth consumption increases
Solution Approach 1:
The patent extracts auxiliary flow tasks from the main packet processing flow and places them in a separate sideband processing track. By taking out these computation-based tasks (acknowledgments, telemetry, congestion control) from the main pipeline, the system improves processing capability for auxiliary tasks while reducing bandwidth consumption in the main packet processing path.
3Device complexity
If completion queue elements are reused for both completion indications and task execution triggers, then device complexity is reduced, but functionality versatility may be limited
Solution Approach 1:
The patent makes completion queue elements universal by enabling them to serve dual purposes: indicating completion of packet processing operations and triggering auxiliary flow tasks in the sideband processor. This multi-functionality reduces device complexity by eliminating the need for separate trigger mechanisms while maintaining versatility through configurable task execution based on CQE content.
Data Source
AI summary
A network device includes a hardware-implemented packet processing pipeline includes: multiple pipeline stages, and a processor. The hardware-implemented packet processing pipeline is to process packets exchanged with a packet network. The processor is to execute sideband tasks for the packet processing pipeline. At least one of the pipeline stages is to trigger the processor to execute a sideband task by posting a Completion-Queue Element (CQE) on a Completion Queue (CQ) accessible to the processor.