Sideband Memory for Variable-Length Packet End Detection
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Solution Overview
Problem
Current methods for processing variable-length packets in buffer memory for transmission in PCI Express integrated circuits face challenges due to high latency and inability to tolerate pipeline stages, leading to difficulties in end-of-packet detection and address determination within a single clock cycle, which prevents the use of external buffer memories.
Innovation Solution
A method and apparatus that utilize a sideband memory to store encoded packet lengths, allowing for efficient end-of-packet determination and address calculation, enabling continuous packet streaming without gaps, even with high-latency buffer memories and external buffer usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a flag is added to the next-to-last word of data in a packet to indicate end-of-packet, then end-of-packet detection can be performed, but the read process must complete detection and address determination in a single clock cycle, which is difficult to meet due to high buffer memory latency
Solution Approach 1:
The patent pre-calculates and stores the address of the next packet in a sideband memory alongside the packet data. When reading a packet, the system simultaneously reads both the packet data and its corresponding next-packet address from the sideband memory in parallel. This preliminary preparation of address information eliminates the need for sequential detection and address calculation, allowing the read process to continue without delay even with high buffer memory latency.
2Productivity
If the current flag-based method is used for end-of-packet detection, then packet transmission can be managed, but the design cannot tolerate any pipeline stages following the buffer memory output, which prevents the use of external buffer memory
Solution Approach 1:
The sideband memory pre-stores the next-packet address information in parallel with the packet data during the write process. This allows the read logic to obtain both the packet data and the next address simultaneously, enabling the insertion of pipeline stages between the buffer memory and subsequent processing logic without causing timing violations. The pre-prepared address information absorbs the additional latency introduced by pipeline stages.
Solution Approach 2:
The sideband memory acts as an intermediary structure that decouples the buffer memory from the read logic. By storing both packet data and next-address information in the sideband memory, it provides a buffer that can tolerate pipeline stages and external memory access delays, enabling greater design flexibility and the use of external buffer memories.
3Quantity of substance
If buffer memory with high latency is used to store packets, then more storage capacity is available, but the high latency makes it difficult to meet the single clock cycle timing requirement for end-of-packet detection and address determination
Solution Approach 1:
The patent separates the packet data storage function from the address determination function. The buffer memory is used solely for storing packet data, while a separate sideband memory stores the next-packet address information. This segmentation allows the use of high-capacity, high-latency buffer memory for data storage while maintaining fast access to address information through the dedicated sideband memory, thus meeting timing requirements despite using slow buffer memory.
Data Source
AI summary
Method and apparatus for processing variable-length packets in a buffer memory for transmission are described. In some examples, as each packet of the packets is written to a buffer memory, a length of the packet is obtained from a length field therein. For each packet of the packets, the length of the packet is compared with a threshold length. An encoded length for each of the packets is stored in a sideband memory, the encoded length for each packet of the packets being: (i) the length of the packet if the length satisfies the threshold; or (ii) a predefined value if the length of the packet does not satisfy the threshold. As each packet of the packets is read from the buffer memory, an end location of the packet is determined responsive to the encoded length thereof in the sideband memory.