Sideband Parity Forwarding Across Point-to-Point Links
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Solution Overview
Problem
As computing systems become increasingly complex, existing interconnect architectures face challenges in meeting bandwidth requirements and balancing performance with power efficiency, particularly in high-performance server environments and mobile devices, where different market segments have distinct demands for interconnect capabilities.
Innovation Solution
The implementation of a layered protocol stack, such as the Peripheral Component Interconnect Express (PCIe) architecture, which utilizes point-to-point links, packetized protocols, and advanced features like power management and error handling to enhance communication efficiency and reliability across various computing platforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple sockets and cores are added to increase processing power, then computing capability is improved, but communication complexity and interconnect demands increase
Solution Approach 1:
The interconnect architecture is segmented into multiple independent lanes or channels, each capable of carrying data independently. This allows parallel communication paths between sockets and cores, distributing the communication load and reducing complexity while maintaining high processing power through multiple cores and sockets.
Solution Approach 2:
The patent introduces additional communication dimensions through layered protocols and multiple interconnect levels. By adding temporal and spatial dimensions to communication (through packetized protocols and credit-based flow control across multiple lanes), the system handles increased complexity without sacrificing performance.
2Productivity
If interconnect bandwidth is increased to meet communication demands, then communication efficiency is improved, but power consumption increases
Solution Approach 1:
The interconnect architecture employs dynamic resource allocation through credit-based flow control, where bandwidth is dynamically adjusted based on actual communication needs rather than being statically maximized. This allows the system to achieve high communication efficiency when needed while reducing power consumption during lower-demand periods.
Solution Approach 2:
The patent utilizes packetized protocols that allow variable data transmission sizes and adjustable lane activation. By changing transmission parameters (packet size, active lanes, data rate) based on communication demands, the system optimizes the balance between communication efficiency and power consumption.
3Device complexity
If traditional multi-drop buses are used for electrical communication, then device complexity is reduced, but communication performance and bandwidth are insufficient
Solution Approach 1:
The traditional multi-drop bus is segmented into multiple independent point-to-point lanes. Each lane operates independently with dedicated signal paths, eliminating the shared bus contention and enabling parallel high-speed communication while maintaining manageable complexity through modular lane design.
Solution Approach 2:
The patent replaces traditional electrical bus communication with a packetized protocol system that uses logical channel abstraction. This substitution allows communication to be decoupled from physical signal constraints, achieving higher performance through software-defined routing and credit-based flow control mechanisms.
Data Source
AI summary
An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.