Sideband Filter-Decimator Tuner With Reduced Multiplier Complexity
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Solution Overview
Problem
Conventional digital tuner-filter-decimators require complex hardware and multipliers for separating digitally sampled signals into upper and lower sideband signals, making them inefficient for multi-channel receivers and requiring significant memory storage registers.
Innovation Solution
A digital filter-decimator-tuner architecture that rearranges filtering and tuning processes, uses symmetric FIR filters, and employs partial sum outputs to reduce hardware requirements, allowing for efficient implementation in Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) with simplified multiplier operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional digital tuner-filter-decimator architecture is used to separate digitally sampled signals into upper and lower sideband signals, then the separation function is achieved, but the hardware complexity and memory storage requirements increase significantly
Solution Approach 1:
The patent inverts the conventional processing sequence by performing decimation before filtering and tuning operations. Instead of filtering then decimating as in traditional architectures, this implementation decimates the input signal first to reduce the sampling rate and signal bandwidth, then applies filtering and tuning operations on the down-sampled signal. This inversion fundamentally reduces the computational complexity and hardware requirements while maintaining signal separation performance.
Solution Approach 2:
The patent segments the complex signal processing task into distinct stages: decimation stage, filtering stage, and tuning stage. By dividing the processing into separate functional blocks that operate on the decimated signal, the system achieves better modularity and reduced complexity compared to the monolithic conventional approach. Each segment can be independently optimized and implemented with simpler hardware.
2Measurement precision
If complex multipliers are used for frequency tuning operations, then accurate frequency separation is achieved, but the hardware implementation becomes more complex and resource-intensive
Solution Approach 1:
The patent changes the operating parameters by working in the decimated domain rather than the full-rate domain. By performing tuning operations on a signal with lower sampling rate and reduced bandwidth, the same frequency separation accuracy can be achieved with simpler multipliers that operate at lower rates. The effective resolution and precision are maintained because the tuning operations are applied after decimation, where the reduced signal bandwidth allows for less complex filter and tuner designs.
Solution Approach 2:
The patent performs decimation as a preliminary action before frequency tuning and filtering operations. This preliminary down-sampling reduces the signal bandwidth and sampling rate, which in turn reduces the complexity of subsequent multiplier operations. The frequency tuning multipliers operate on a lower-rate signal, requiring fewer computational resources while maintaining the same frequency separation accuracy.
3Reliability
If filtering is performed before decimation in conventional architecture, then anti-alias filtering is provided, but the filter complexity and memory requirements increase
Solution Approach 1:
The patent inverts the conventional filter-then-decimate sequence by performing decimation first, then applying filtering operations on the decimated signal. This inversion allows the use of shorter, simpler filters that operate at the lower post-decimation sampling rate. The anti-aliasing function is effectively provided by the decimation process itself, combined with the subsequent filtering, requiring fewer memory storage registers and less complex filter implementations compared to conventional full-rate filtering.
Data Source
AI summary
A digital filter-decimator-tuner is configured to receive a complex signal input xk and output a complex USB signal yuk and a complex LSB signal ylk. It includes a USB processing path coupled to receive xk and output yuk, the USB processing path including a USB FIR filter configured to receive a portion of the xk signal and output a first USB intermediate filtered signal, a decimator configured to decimate the first USB intermediate filtered signal and output a second USB intermediate signal, a USB tuner configured to receive the second USB intermediate signal and a USB tuning signal and output a third USB intermediate signal, and a USB equalization filter configured to receive the third USB intermediate signal, and output yuk; and a parallel LSB processing path coupled to receive xk and output ylk. The USB and LSB processing paths may be implemented by the same hardware in one embodiment.