Sidewall Interconnection Structure for 3D Stacked Semiconductors
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Solution Overview
Problem
The continuous miniaturization of semiconductor devices makes it challenging to manufacture high-density interconnection structures, particularly in the lateral direction, and there is a need for flexible interconnections in stacked multilayer devices to increase integration levels.
Innovation Solution
A semiconductor apparatus with a sidewall interconnection structure is developed, featuring a conductive structure within an electrical isolation layer, allowing for electrical connections between stacked semiconductor devices at different heights, which reduces the number of photolithography steps and manufacturing costs, and enables a three-dimensional configuration for low resistance and high bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar interconnection structures are used, then manufacturing process is simpler, but integration density and bandwidth are limited
Solution Approach 1:
The patent transitions from planar (2D) interconnection structures to three-dimensional (3D) sidewall interconnection structures. Conductive structures are formed on the sidewalls of semiconductor devices at multiple heights, enabling vertical stacking and significantly increasing integration density while maintaining manageable manufacturing complexity through standardized formation processes.
2Manufacturing precision
If more photolithography steps are used, then interconnection precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent employs selective etching to pre-form sidewall surfaces on semiconductor devices before depositing conductive materials. This preliminary structuring enables precise interconnection formation through subsequent conformal deposition and planarization steps, achieving high precision while reducing the total number of photolithography steps required.
Solution Approach 2:
The sidewall interconnection structures utilize the device sidewalls themselves as natural alignment references. The conductive structures are formed conformally on these sidewalls, automatically achieving precise spatial registration with the underlying devices without requiring additional alignment steps, thereby reducing manufacturing cost while maintaining precision.
3Area of moving object
If lateral size is reduced, then device density is improved, but interconnection manufacturing becomes more difficult
Solution Approach 1:
The patent addresses lateral scaling challenges by moving interconnection formation to the vertical dimension. Instead of routing interconnections laterally across miniaturized devices, conductive structures are formed on sidewalls at multiple vertical levels, allowing high-density interconnection in vertically stacked configurations that are insensitive to lateral device size reduction.
Data Source
AI summary
Disclosed are a semiconductor apparatus with a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device. The semiconductor apparatus includes: a plurality of device stacks, wherein each device stack includes a plurality of semiconductor devices stacked, and each semiconductor device includes a first source/drain layer, a channel layer, and a second source/drain layer stacked in a vertical direction, and a gate electrode surrounding the channel layer; and an interconnection structure between the plurality of device stacks. The interconnection structure includes: an electrical isolation layer; and a conductive structure in the electrical isolation layer. At least one of the first source/drain layer, the second source/drain layer, and the gate electrode of each of at least one of the semiconductor devices is in contact with and thus electrically connected to the conductive structure at a corresponding height in the interconnection structure in a lateral direction.