3D Stacked Die Sidewall Antenna Arrays for Better Decoupling
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Solution Overview
Problem
Conventional wafer-level antenna arrays for semiconductor packages constrain radiation patterns, die orientation, and package size, especially when operating at sub-terahertz frequencies, as they are typically limited to the top surface of the die or 3D stacked die package, restricting the implementation of multiple antenna arrays and efficient use of die space.
Innovation Solution
The integration of antenna arrays on the side walls of a 3D stacked die package, where multiple die layers are bonded together to form a 3D cube structure with exposed antenna elements, allowing for improved decoupling and efficient use of die space, enabling the realization of ultra-high frequency antenna arrays for sub-THz frequencies like 300 GHz and above.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wafer-level antenna arrays are implemented on the top surface of the die, then antenna arrays can be integrated at the wafer level, but radiation patterns are constrained and die orientation is limited
Solution Approach 1:
The patent transitions antenna array placement from the traditional two-dimensional top surface of the die to the three-dimensional side walls of the 3D stacked die package. This dimensional change enables antenna elements to be positioned on multiple faces of the package, providing flexible radiation patterns and orientation control while maintaining wafer-level integration benefits.
2Ease of manufacture
If conventional wafer-level antenna arrays are used, then integration is achieved, but package size is constrained and multiple antenna arrays cannot be efficiently implemented
Solution Approach 1:
The patent embeds multiple antenna arrays within the side walls of a single 3D stacked die package, utilizing the internal three-dimensional space efficiently. Multiple antenna elements are nested along the vertical and lateral dimensions of the package sides, enabling multiple arrays to coexist in a compact footprint without increasing overall package size.
Solution Approach 2:
By moving antenna arrays to the side walls and utilizing the third dimension (vertical stacking), the patent increases the effective area available for antenna placement without expanding the package footprint. This enables multiple antenna arrays to be implemented within the same lateral footprint by stacking them vertically along the side walls.
3Ease of manufacture
If antenna arrays are placed on the top surface, then wafer-level integration is achieved, but decoupling between arrays is insufficient
Solution Approach 1:
The patent positions antenna arrays on opposite or adjacent side walls of the 3D stacked package, utilizing spatial separation in three dimensions. This lateral and vertical separation between antenna arrays on different faces of the package provides natural electromagnetic decoupling, reducing mutual interference while maintaining the benefits of wafer-level integration.
Data Source
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AI summary
A semiconductor package with integrated side wall antennas is provided. An apparatus includes two or more die layers that are bonded together, each of the two or more die layers comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes a first antenna array, the first antenna array comprising a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements is at least partially exposed at the first side wall.