Semiconductor Package Sidewall Bonding Tape for Power Integrity
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Solution Overview
Problem
High-speed semiconductor devices face power/ground noise issues due to increasing parasitic inductance, which affects their performance, and existing solutions do not adequately address these noise problems.
Innovation Solution
A semiconductor package structure is developed with a decoupling capacitor positioned adjacent to the semiconductor chip using a vertical chip interconnection (VCI) to reduce inductance and improve power integrity, where bonding tapes and wires electrically connect the capacitor to the chip, reducing noise and stabilizing power/ground voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a decoupling capacitor is added on the substrate surface to stabilize power/ground voltage, then power integrity is improved, but parasitic inductance increases due to the distance between the capacitor and semiconductor chip
Solution Approach 1:
The bonding tape is extended to contact the sidewall of the semiconductor chip, transitioning from a conventional planar connection to a three-dimensional configuration. This allows the decoupling capacitor to be electrically connected to the chip through the sidewall, reducing the current path length and parasitic inductance while maintaining power integrity
Solution Approach 2:
The bonding tape serves as an intermediary element that bridges the decoupling capacitor and the semiconductor chip. By extending the bonding tape to contact the chip sidewall, it creates a direct electrical connection that minimizes inductance, effectively mediating between the capacitor and chip
2Object-affected harmful factors
If the bonding tape is extended to contact the sidewall of the semiconductor chip, then parasitic inductance is reduced, but manufacturing complexity increases
Solution Approach 1:
The bonding process is segmented into distinct regions: the bonding tape contacts the substrate at one end and extends to contact the chip sidewall at another end. This segmentation allows for standardized bonding procedures while achieving the complex three-dimensional connection geometry
Solution Approach 2:
The bonding tape configuration changes from a conventional planar arrangement to an extended three-dimensional structure. By modifying the geometric parameters of the bonding tape (extending it to contact the sidewall), the electrical performance is improved while the manufacturing process remains compatible with existing bonding technologies
Data Source
AI summary
A semiconductor package having a structure in which a decoupling capacitor is disposed to be adjacent with a semiconductor chip using a vertical chip interconnection (VCI) to improve power integrity. The semiconductor package includes a semiconductor substrate including a first finger pad and a second finger pad, a semiconductor chip mounted on the semiconductor substrate and including a first chip pad and a second chip pad, a bonding tape electrically connecting the first finger pad and the first chip pad, and a bonding wire electrically connecting the second finger pad and the second chip pad. Here, the bonding tape is formed to make contact with a sidewall of the semiconductor chip in a vertical direction of the semiconductor chip.