Substrate-less Semiconductor Package with Sidewall Conductive Interconnects
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Solution Overview
Problem
Conventional semiconductor packages face limitations in design flexibility and miniaturization due to the need for substrates and wire bonding, which can lead to increased footprint and reduced reliability.
Innovation Solution
The semiconductor package employs a TSW (SideWall) configuration where dies are stacked vertically with conductive patterns on their sidewalls, allowing for the attachment of additional components without a substrate, using conductive patterns and connectors to form a redistribution layer for electrical interconnection, thereby eliminating wire bonds and enhancing bonding strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional substrate-based packaging with wire bonding is used, then electrical interconnection is achieved, but package footprint is increased and design flexibility is reduced
Solution Approach 1:
The patent extracts and eliminates the substrate from the packaging structure, transitioning from a substrate-based configuration to a substrate-less die-stack configuration. This removal of the substrate directly reduces package footprint while enabling greater design flexibility through alternative interconnection methods.
Solution Approach 2:
The patent transitions from planar 2D packaging on a substrate to 3D vertical stacking of dies. By arranging dies in a vertical stack and using sidewall conductive patterns for interconnection, the package achieves reduced footprint while maintaining or enhancing functionality through three-dimensional spatial utilization.
2Reliability
If wire bonding is used for electrical interconnection, then connectivity is achieved, but bonding strength is reduced and reliability is decreased
Solution Approach 1:
The patent replaces the mechanical wire bonding process with direct conductive pattern interconnection through sidewall contacts. This substitution eliminates the need for fragile wire bonds and associated bonding processes, thereby enhancing bonding strength and reliability while simplifying the overall device structure.
3Volume of moving object
If substrate-based packaging is used, then structural support is provided, but package size is increased and miniaturization is limited
Solution Approach 1:
The patent implements a nested configuration where multiple dies are stacked vertically within a compact volume. The sidewall conductive patterns are nested within the die structure itself, eliminating the need for an external substrate. This nesting approach minimizes package volume while maintaining structural integrity through the stacked architecture.
Data Source
AI summary
The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.