Sidewall Conductor Layout for Compact Semiconductor Packaging
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Solution Overview
Problem
Conventional semiconductor packages face issues of high cost, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
A semiconductor device structure comprising a dielectric and conductive material configuration with specific top, side, and bottom sections, along with a protective encapsulant, is used to form a compact and reliable semiconductor package. This configuration includes a dielectric top section over the device top side, a dielectric side section continuous with the top section, and a dielectric bottom section coplanar with the device bottom side, along with a conductive structure that is electrically connected to terminals and interconnects, all encapsulated by a protective material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor package structures are used, then manufacturing is simpler, but package size becomes too large
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to a three-dimensional vertical architecture. Multiple conductive layers (first conductive layer, second conductive layer) are stacked vertically with dielectric layers in between, enabling compact integration while maintaining electrical connectivity. The side wall structure extending vertically provides mechanical support and defines the compact package footprint.
Solution Approach 2:
The patent implements nested structures where conductive layers are embedded within dielectric layers, and dielectric layers are positioned between conductive layers. The side wall structure is nested within the overall package architecture, providing structural support while occupying minimal space. This nested arrangement achieves high integration density in a compact volume.
2Ease of manufacture
If conventional semiconductor packages are used, then manufacturing processes are simpler, but cost increases
Solution Approach 1:
The patent divides the package into distinct functional segments: conductive layers for electrical connectivity, dielectric layers for insulation and structural support, and a side wall structure for mechanical integrity. This segmentation allows each component to be optimized independently while maintaining overall reliability and enabling standardized manufacturing processes for each layer type.
Solution Approach 2:
The patent employs composite material structures combining conductive materials (for electrical pathways) with dielectric materials (for insulation and mechanical support). The side wall structure uses composite construction to provide both structural integrity and electrical isolation. This composite approach enhances reliability while maintaining manufacturing feasibility through established material processing techniques.
3Reliability
If conventional semiconductor packages are used, then device performance is adequate, but reliability decreases
Solution Approach 1:
The patent achieves enhanced reliability through vertical stacking of multiple conductive and dielectric layers, creating a three-dimensional architecture that provides redundant electrical pathways and improved thermal management. The side wall structure extends vertically to provide comprehensive mechanical support and environmental protection, increasing package robustness without excessive horizontal footprint.
Solution Approach 2:
The dielectric layers are positioned between conductive layers to provide electrical isolation and mechanical cushioning before stress or environmental damage can occur. The side wall structure is formed beforehand to protect internal layers from mechanical damage and environmental factors, enhancing reliability through preventive structural design.
Data Source
AI summary
In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.