Patterned Sidewall Conductors for Stacked Microelectronic Packages
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Solution Overview
Problem
Conventional 3D microelectronic packaging technologies face limitations in efficiency, cost-effectiveness, and scalability due to the need for complex interconnection methods like BGAs, which increase manufacturing complexity and vertical device profile.
Innovation Solution
A method for fabricating stacked microelectronic packages using patterned sidewall conductors formed on pre-singulated device panels, where microelectronic device panels are laminated and trenches are created to deposit electrically-conductive materials, which are then patterned to interconnect package layers, reducing the reliance on BGAs and enhancing layer-to-layer connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D packaging technologies use BGAs for vertical interconnection, then electrical connectivity between package layers is achieved, but manufacturing complexity and vertical device profile increase
Solution Approach 1:
The patent transitions from conventional BGA interconnection to sidewall conductors formed on the vertical sidewalls of trenches. This dimensional change allows electrical interconnection to occur on the sidewall surface rather than requiring vertical penetration through the package substrate, thereby reducing manufacturing complexity while maintaining connectivity.
Solution Approach 2:
The patent segments the interconnection function by separating the conductor formation from the substrate penetration. Sidewall conductors are formed independently on trench sidewalls and then connected to top and bottom conductors, dividing the complex BGA interconnection process into manageable segments that reduce overall manufacturing complexity.
2Reliability
If conventional 3D packaging technologies use BGAs for vertical interconnection, then electrical connectivity between package layers is achieved, but vertical device profile increases
Solution Approach 1:
The patent utilizes the vertical sidewall dimension for conductor placement, allowing interconnection to occur laterally along the trench wall rather than requiring extended vertical penetration. This reduces the vertical profile requirement while achieving the same electrical connectivity function.
3Ease of manufacture
If 2D packaging approach is used, then manufacturing process is simpler, but package compactness and interconnection length are reduced
Solution Approach 1:
The patent adopts 3D stacking with sidewall conductors formed on vertical trench sidewalls, enabling vertical integration of multiple package layers. This three-dimensional arrangement achieves compact packaging while the sidewall conductor formation process maintains manufacturing simplicity by using standard semiconductor fabrication techniques.
Data Source
AI summary
Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.