Sidewall Conductors for Stacked Microelectronic Packages
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Solution Overview
Problem
Traditional microelectronic packaging methods are limited by their two-dimensional approach, which results in bulky and inefficient interconnections between stacked microelectronic devices, leading to increased signal delay and reduced compactness in electronic devices.
Innovation Solution
The use of uniquely-formed sidewall conductors that eliminate or reduce the need for Ball Grid Arrays (BGAs) and other contact formations, providing electrically-conductive paths between package layers and protecting against damage during manufacturing and transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional two-dimensional packaging methods are used, then ease of manufacture is maintained, but device compactness and interconnection efficiency deteriorate
Solution Approach 1:
The patent transitions from traditional two-dimensional packaging to three-dimensional stacked packaging, where multiple package layers are vertically arranged and interconnected through sidewall conductors. This dimensional change enables compact vertical integration while maintaining manufacturing simplicity through standardized stacking processes.
2Reliability
If Ball Grid Arrays and contact formations are used for interconnection, then electrical connectivity is achieved, but vulnerability to damage during manufacturing and transport increases
Solution Approach 1:
The patent extracts the vulnerable BGA contact formations from the interconnection structure and replaces them with sidewall conductors that are embedded within the package layers. This extraction eliminates the exposed contact points that are susceptible to damage during handling and transport.
Solution Approach 2:
The sidewall conductors are positioned within the package structure before final assembly, providing inherent mechanical protection. The surrounding package materials act as cushioning that protects the conductive paths from damage during subsequent manufacturing steps and transport.
3Loss of time
If vertical stacking of microelectronic devices is implemented, then signal delay is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the stacked package into discrete layers with standardized interfaces. Each layer can be manufactured and prepared independently, then stacked and interconnected through systematic processes. This segmentation reduces the overall manufacturing complexity despite the three-dimensional configuration.
Data Source
AI summary
A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic layers. Saw streets of the first package layer overlie and are aligned with saw streets of the second package layer. The first and second package layers include respective edge connectors formed between the saw streets and electronic components in the first and second package layers. A through package via is formed in one of the saw streets of the first and second package layers. The via is filled with conductive material. The stacked package layers are singulated along the saw streets in a manner that retains a portion of the conductive material to form a sidewall connector between at least two of the edge connectors.