Sidewall Fill Frontside Contact for Aligned Stacked FET Connections
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Solution Overview
Problem
The formation of contact structures connecting source/drain regions of stacked FET devices to buried power rails or signal lines in high-density semiconductor devices faces challenges such as increased contact resistance and misaligned connections due to reduced cell height.
Innovation Solution
A fill frontside contact structure is formed to contact the side surfaces of upper and lower source/drain patterns, isolated by side spacers, to facilitate connections between stacked FET devices, reducing misalignment and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cell height is reduced to increase device density, then device density is improved, but contact resistance increases and alignment precision deteriorates
Solution Approach 1:
The contact structure transitions from a conventional planar contact to a fill frontside contact that extends vertically along the side surface of the source/drain pattern. This dimensional change allows the contact to reach the source/drain region despite the reduced cell height, maintaining low contact resistance while enabling higher device density.
Solution Approach 2:
The contact structure is divided into multiple segments: a fill frontside contact portion extending along the side surface, a top surface contact portion, and intermediate portions connecting them. This segmentation allows each part to fulfill specific functions - the side contact provides vertical access, while the top surface contact ensures electrical connection, collectively solving the alignment and resistance issues.
2Productivity
If cell height is reduced to increase device density, then device density is improved, but alignment precision deteriorates
Solution Approach 1:
The fill frontside contact structure is configured to self-align with the source/drain pattern through its geometric relationship. The contact extends along the side surface of the source/drain pattern, and its position is determined by the source/drain pattern itself rather than requiring separate alignment processes, thereby maintaining high alignment precision despite reduced cell height.
Solution Approach 2:
The contact structure exhibits asymmetric geometry with different configurations at the top surface versus the side surface. The fill frontside contact portion extends vertically along the side, while the top surface contact portion has a different shape optimized for electrical connection. This asymmetric design allows the contact to adapt to the reduced cell height while maintaining precise alignment with the source/drain pattern.
3Ease of manufacture
If conventional contact structures are used in reduced cell height devices, then manufacturing process remains simple, but contact resistance increases and connections become misaligned
Solution Approach 1:
The fill frontside contact structure serves multiple functions simultaneously: it provides vertical access to the source/drain region, ensures electrical connection through the top surface contact portion, and maintains alignment through self-alignment with the source/drain pattern. This multi-functionality allows a single contact structure to address multiple issues that would otherwise require separate components or processes.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
Provided is a semiconductor device which includes: a 1st field-effect transistor, FET, including a 1st source/drain pattern; a 2nd FET including a 2nd source/drain pattern, vertically above the 1st FET; a 1st side spacer on a right surface of the 1st source/drain pattern, the 1st side spacer comprising an isolation material; and a frontside contact structure on a right surface of the 2nd source/drain pattern and a right surface of the 1st side spacer, wherein the frontside contact structure is connected to the 2nd source/drain pattern and is isolated from the 1st source/drain pattern by the 1st side spacer.