Sidewall Diode Driving Device for High-Density Memory
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Solution Overview
Problem
The scalability of high-density memory devices is hindered by the complex manufacturing technology required for diode driving devices, which often necessitates advanced lithography tools and multiple patterning processes, making it difficult to produce diodes on small scales effectively.
Innovation Solution
The use of sidewall diode driving devices with a P-N junction in a semiconductor layer, where the diode includes first and second terminals with a P-N junction in between, positioned on a patterned insulating layer, allowing for a more scalable and efficient manufacturing process by reducing the need for advanced patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional line patterning or hole fill-in technology is used to manufacture diode driving devices, then the diodes can function as driving devices in memory cells, but the manufacturing process requires advanced lithography tools and multiple patterning processes, making it difficult to scale to small dimensions
Solution Approach 1:
The patent transitions from planar diode structures to three-dimensional vertically-aligned diode structures. The diode is formed by depositing alternating doped and intrinsic semiconductor layers in the vertical dimension, allowing the P-N junction to be created without complex lateral patterning. This vertical stacking approach enables scaling to smaller dimensions while simplifying the manufacturing process.
Solution Approach 2:
The diode structure is segmented into multiple thin layers with alternating doping types (n-type and p-type) separated by intrinsic layers. This segmentation into discrete functional layers allows each layer to be deposited independently using standard semiconductor fabrication techniques, avoiding the need for advanced lithography and multiple patterning processes.
2Productivity
If advanced lithography tools and multiple patterning processes are used to manufacture diodes on small scales, then higher density memory devices can be produced, but the manufacturing complexity and costs increase significantly
Solution Approach 1:
The vertically-aligned diode structure is self-aligned by default, as the alternating semiconductor layers are deposited conformally on top of each other without requiring additional alignment steps. The intrinsic layers automatically serve as barriers and junction interfaces, eliminating the need for complex alignment procedures associated with advanced lithography.
Solution Approach 2:
The patent changes the fundamental manufacturing parameters from lateral patterning dimensions to vertical layer thickness dimensions. By controlling the thickness of each deposited layer rather than relying on lithographic patterning, the process becomes scalable using standard deposition equipment, significantly improving ease of manufacture while maintaining high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high-density memory devices with improved scalability, reducing manufacturing complexity and costs while maintaining the functionality of diode driving devices in phase change memory arrays.
Implementation Method 1
The diode acts as a driving device, so that memory cells can be selected for operation by forward bias on the diode, while current flow in unselected memory cells is blocked by reverse bias on the diode.
Implementation Method 2
an electrical current pulse with a large magnitude for a short time period can be used to heat up an active region of the memory element to a melting temperature, and then cause it to solidify in the amorphous phase
Implementation Method 3
an electrical current pulse with a medium magnitude, which causes it to heat up to a crystallization transition temperature, and a longer time period can be used allowing the active region to solidify in a crystalline phase
Implementation Method 4
The phase change memory element is made of phase change materials that exhibit a large resistivity contrast between crystalline (low resistivity) and amorphous (high resistivity) states.
Data Source
AI summary
A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.