Sidewall Floating Gate Memory Device Preventing Over-Erase

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Solution Overview

Problem

Existing embedded flash memory devices face an over-erase phenomenon during erase operations, which requires additional recovery operations and increases peripheral circuit size, and incorporating a select gate to prevent this often doubles the unit cell size.

Innovation Solution

A non-volatile memory device with a select gate and independently programmable floating gates formed on the sidewalls of the select gate, using methods like Fowler-Nordheim tunneling and hot carrier injection for programming and erasing, without the need for additional recovery operations or increased peripheral circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a select gate is disposed in each cell to prevent over-erase phenomenon, then reliability is improved, but area of unit cell increases

Engineering Contradiction:

Improveprevention of over-erase phenomenonVSAvoidunit cell size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the select gate structure with the word line structure, making the select gate function as part of the word line. This integration allows the select gate to prevent over-erase phenomena while sharing the same structural framework as the word line, thereby reducing the additional area that would be required for a completely separate select gate structure in each cell.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The select gate is designed to serve multiple functions: it acts as both a selection mechanism for specific memory cells and as part of the word line structure. This multi-functionality allows the same structure to perform both selection and over-erase prevention without requiring additional dedicated structures, thus maintaining area efficiency while improving reliability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If additional recovery operation is performed to solve over-erase phenomenon, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvecorrection of over-erase phenomenonVSAvoidperipheral circuit size

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The select gate structure is designed to preemptively prevent the over-erase phenomenon from occurring in the first place, rather than requiring subsequent recovery operations. By controlling the erase operation at the cell level through the select gate, the patent eliminates the need for additional recovery circuits and operations, thereby improving reliability while reducing device complexity.

Inventive Principle:

Principle #9Preliminary anti-action

3Productivity

If floating gates are formed on sidewalls of select gate for independent programming, then productivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveindependent programming capabilityVSAvoidfloating gate positioning

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces charge blocking layers as intermediary structures between the select gate and the floating gates. These charge blocking layers serve as precise positioning templates that guide the formation of floating gates on the sidewalls of the select gate. By using this intermediary structure, the patent achieves high positioning precision for the floating gates while maintaining a manufacturable process flow that supports independent programming capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents over-erase phenomena without additional operations, maintains the degree of integration, and offsets the area increase due to the select gate by allowing independent programming of floating gates, enhancing operating characteristics and integration.

Implementation Method 1

The plurality of floating gates may be erased through the use of a Fowler-Nordheim (FN) tunneling method.

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Implementation Method 2

A floating gate adjacent to any one of the plurality of junctions may be performed through the use of a hot carrier injection (HCI) method.

Methodology Applied

Scientific EffectHot carrier injection:

Data Source

PatentUS9171622B2Non-volatile memory device and method of fabricating the same

Publication Date: 2015.10.27 SK HYNIX INC

AI summary

This technology provides a non-volatile memory device and a method of manufacturing the same, which may prevent an over-erase phenomenon and also increase the degree of integration, In an aspect, the non-volatile memory device includes a select gate formed over a substrate, a plurality of floating gates laterally formed with respect to the select gate and spaced apart from each other, to be independently programmable, and a plurality of junctions formed in the substrate and arranged to be controllable by the respective floating gates.