Sidewall Floating Gate Non-Volatile Memory for Low Voltage Operation
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in reducing operational voltage and increasing reliability due to the miniaturization of memory cells, which leads to undesired electrical punch-through and degradation of the tunneling oxidation layer, affecting performance and integrity.
Innovation Solution
The proposed non-volatile memory device incorporates a stack structure with a floating gate, tunneling dielectric layer, erase gate dielectric layer, auxiliary gate dielectric layer, and a control gate, where the floating gate is positioned on the sidewall with a corner portion adjacent to the erase gate, and the control gate covers the floating gate to increase the coupling ratio, reducing operational voltage and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate length is reduced to miniaturize memory cells, then the device size is reduced and integration is improved, but the channel length below the tunneling oxidation layer is reduced which induces electrical punch-through between drain and source regions
Solution Approach 1:
The gate structure is segmented into a control gate and a floating gate that are spatially separated. The control gate is positioned above the source region while the floating gate is positioned on the sidewall of the stack structure. This segmentation allows the control gate to be optimized for control function while the floating gate handles charge storage, preventing electrical punch-through in the miniaturized channel region.
Solution Approach 2:
The floating gate is positioned on the sidewall of the stack structure rather than above the channel, utilizing the vertical dimension and sidewall space. This three-dimensional positioning increases the gate-coupling ratio without reducing the channel length, thereby preventing electrical punch-through while maintaining miniaturization benefits.
2Productivity
If electrons repetitively pass through the tunneling oxidation layer during programming and erasing operations, then data storage function is achieved, but the quality of the tunneling oxidation layer decreases and reliability is reduced
Solution Approach 1:
The floating gate acts as an intermediary between the control gate and the tunneling oxidation layer. Electrons are injected into the floating gate from the source region through hot electron injection, and then coupled to the control gate through the inter-gate dielectric layer. This intermediary mechanism reduces the number of times electrons must tunnel through the tunneling oxidation layer, preserving its quality while maintaining programming and erasing functionality.
3Productivity
If the gate-coupling ratio is increased to reduce operational voltage and improve speed, then operational efficiency is improved, but the device structure becomes more complex
Solution Approach 1:
The control gate and floating gate are merged into a single integrated structure where the floating gate is positioned on the sidewall of the stack structure and the control gate is positioned above the source region. This merging allows the two gates to work together as a unified system, achieving high gate-coupling ratio and low operational voltage without proportionally increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the operational voltage required to turn on/off the channel region, increases the coupling ratio, and improves the speed and reliability of programming and erasing operations by concentrating the electrical field, thereby enhancing the overall integrity and performance of the memory device.
Implementation Method 1
The tunneling dielectric layer is disposed between the floating gate and the substrate
Implementation Method 2
a top portion of the floating gate has a corner portion, the corner portion is adjacent to the erase gate, and a height of the corner portion falls within a range of a height of the erase gate
Data Source
AI summary
A non-volatile memory having memory cells is provided. The memory cells include stack structures, floating gates, tunneling dielectric layers, erase gate dielectric layers, auxiliary gate dielectric layers, source regions, drain regions, control gates and inter-gate dielectric layers. The stacked structures include gate dielectric layers, auxiliary gates, insulating layers and erase gates. The floating gates are disposed on sidewalls on a first side of the stacked structures. The tunneling dielectric layers are disposed under the floating gates. The erase gate dielectric layers are disposed between the erase gates and floating gates. The auxiliary gate dielectric layers are disposed between the auxiliary gates and the floating gates. The source and drain regions are separately disposed on sides of the stack structures and the floating gates. The control gates are disposed on the source regions and the floating gates. The inter-gate dielectric layers are disposed between the control gates and the floating gates.