Self-Aligned Sidewall Gate GaN HEMT Fabrication
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Solution Overview
Problem
Existing methods for fabricating GaN HEMTs face challenges with poor gate length uniformity, increased process cost, reduced throughput, and high parasitic capacitances due to limitations in e-beam lithography and ohmic contact resistances, necessitating a method for ultra-short, high aspect ratio gates and source-drain spacings with improved reproducibility and reduced access resistance.
Innovation Solution
A process involving multiple epitaxial layers, dielectric films, and reactive ion etching to form sidewall gates and spacers, allowing for precise control of gate length and source-drain spacing through optical lithography, and regrowth of low-resistance ohmic contacts, enhancing gate aspect ratios and reducing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If e-beam lithography is used for gate foot and head definition, then gate length can be controlled, but gate length uniformity is poor and process cost increases
Solution Approach 1:
The patent replaces e-beam lithography with optical lithography combined with self-aligned sidewall spacer formation. The gate length is defined by the thickness of deposited dielectric spacers rather than direct lithographic patterning, achieving superior uniformity (sub-10nm) while using lower-cost optical lithography equipment.
Solution Approach 2:
The sidewall spacers automatically define the gate length through conformal deposition on the source and drain regions. The process is self-aligning, eliminating the need for complex e-beam lithography steps and achieving consistent gate lengths without additional alignment procedures.
2Manufacturing precision
If e-beam lithography is used for gate definition, then gate length can be defined, but process throughput is reduced
Solution Approach 1:
The patent substitutes time-consuming e-beam lithography with faster optical lithography followed by conformal dielectric deposition. The self-aligned spacer formation process defines gate length through deposition thickness control rather than slow lithographic patterning, dramatically increasing manufacturing throughput.
3Manufacturing precision
If lithographic definition of source-drain spacing is used, then spacing can be defined, but device dimensions are limited and access resistance increases
Solution Approach 1:
The sidewall spacers automatically define the source-drain spacing through self-aligned deposition. This enables precise nanometer-scale control of spacing while minimizing the distance between source/drain contacts and the channel, thereby reducing access resistance and improving device reliability.
4Ease of manufacture
If conventional lithography is used for gate patterning, then process cost is reduced, but gate aspect ratio is limited and parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar gate patterning to three-dimensional sidewall gate formation. The gate is defined vertically along the sidewalls of the source and drain regions, enabling high aspect ratios that reduce the gatehead-to-channel distance and minimize parasitic gate capacitances while maintaining compatibility with optical lithography.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process achieves ultra-short gate-length devices with high aspect ratios and nanometer-scale source-drain spacings, improving uniformity, reducing access resistances, and increasing throughput while lowering costs compared to conventional e-beam lithography.
Implementation Method 1
reactive ion etching the third epitaxial layer with recess into the second epitaxial layer in order to allow contact between a 2DEG and regrown n+ ohmic contacts
Implementation Method 2
growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer
Data Source
AI summary
A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.