Sidewall Image Transfer Fin Patterning for Sub-20 nm Pitch
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Solution Overview
Problem
Current methods struggle to fabricate fin structures with sub-30 nm or sub-20 nm fin pitches in FinFET fabrication, as existing sidewall image transfer (SIT) processes are not practical for achieving such tight pitches without resorting to complex and expensive EUV lithography or double/triple patterning techniques.
Innovation Solution
A method involving a fin-patterning process using a substrate with multiple hard-mask layers and spacer materials, where trench openings are formed and filled with hard-mask mandrels, followed by spacer deposition and etching to create sidewall spacers, allowing for the formation of fin structures with pitches below 20 nm using ArF deep UV immersion lithography and chemical vapor deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography methods are used, then manufacturing cost is reduced, but fin pitch cannot achieve sub-30 nm or sub-20 nm dimensions
Solution Approach 1:
The patent divides the patterning process into multiple stages: first forming initial mandrels, then depositing spacers on mandrel sidewalls, removing mandrels, and repeating the process to create progressively finer features. This segmentation enables achieving sub-20 nm fin pitch through iterative refinement rather than requiring single-step high-resolution lithography.
Solution Approach 2:
The patent transitions from planar lithographic patterning to three-dimensional sidewall spacer formation. By depositing conformal spacer layers on the vertical sidewalls of mandrels and using anisotropic etching, the process creates features in the vertical dimension that translate to ultra-fine horizontal pitch, bypassing the diffraction limits of conventional lithography.
2Manufacturing precision
If EUV lithography is adopted to achieve sub-30 nm fin pitch, then manufacturing precision is improved, but equipment cost and power consumption increase significantly
Solution Approach 1:
The patent creates copies of the original mandrel pattern through conformal spacer deposition. Each spacer layer replicates the mandrel geometry with precise dimensional control, enabling multiplication of the original lithographic pattern density. This copying approach achieves ultra-fine pitch using existing ArF lithography tools rather than requiring expensive EUV equipment.
Solution Approach 2:
The patent changes the physical parameters of the patterning process by transitioning from direct optical lithography to a multi-step process involving atomic layer deposition (ALD) of spacers and selective etching. This parameter change enables precise control of fin pitch at sub-20 nm scale using conventional lithography wavelengths, avoiding the need for EUV lithography infrastructure.
3Manufacturing precision
If double or triple patterning techniques are used, then fin pitch is reduced, but process complexity and manufacturing time increase
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial mandrels and conformal spacer layers before the final etching step. The spacer layers are deposited with precise thickness control using ALD, and mandrels are removed in advance to create clean sidewall profiles. This preliminary preparation enables the final etch to produce accurate sub-20 nm fins in a single step, reducing total process time compared to iterative patterning methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the practical fabrication of FinFET devices with fin pitches below 20 nm, offering improved scalability and cost-effectiveness compared to EUV lithography, while maintaining precise control over feature size and pitch, thus addressing the limitations of existing SIT processes.
Implementation Method 1
chemical vapor deposition processes
Data Source
AI summary
A method of using sidewall image transfer (SIT) process to pattern fin structures is provided. The method includes providing a fin-patterning substrate containing a first hard-mask layer and a second hard-mask layer over a semiconductor substrate. Trench openings formed on the semiconductor substrate extending vertically through the first hard-mask layer and the second hard-mask layer. Trench openings are filled with a third hard-mask material. The second hard-mask layer is removed to reveal hard-mask mandrels. First sidewall spacers are formed on the opposite sides of the hard-mask mandrels using atomic layer deposition (ALD) process. The semiconductor substrate is etched using the first sidewall spacers and the hard-mask mandrels as mask, subsequently the spacers, the mandrels and the hard-mask layer are removed to reveal fin structures. The method of the present invention is to form fins at a very tight fin pitch by using the very tight thickness controllability of ALD process. By repeating the ALD step twice or more to form multiple SIT spacers the fin pitch size can be reduced further. The inventive method is suitable for fabricating tight fin pitch to less than about 20 nm.