Self-aligned fine pitch interconnects via sidewall image transfer
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Solution Overview
Problem
Traditional dual-damascene integration processes in semiconductor manufacturing are complex, costly, and prone to dielectric damage, leading to reliability issues and increased manufacturing time due to the need for multiple sacrificial hardmask layers and plasma etching, which degrades the performance and yield of interconnect structures.
Innovation Solution
The implementation of a single-damascene and dual-damascene interconnect structure fabrication method that eliminates the need for reactive ion etching and reduces the number of sacrificial materials by using sidewall image transfer techniques, conformally depositing interlevel dielectric layers, and minimizing plasma etching, thereby simplifying the process and reducing dielectric damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional dual-damascene integration process is used with multiple sacrificial hardmask layers and plasma etching, then interconnect structures can be formed, but process complexity increases and dielectric damage occurs leading to reliability issues
Solution Approach 1:
The patent removes sacrificial hardmask layers from the process, extracting the harmful element that causes dielectric damage. The sidewall image transfer technique forms patterns directly in the dielectric material without requiring separate sacrificial layers, thereby eliminating the source of process-induced dielectric damage while maintaining the ability to form interconnect structures
Solution Approach 2:
The patent eliminates the need to deposit and remove multiple sacrificial hardmask layers by using sidewall image transfer. The mandrel structures are removed after transferring their pattern to the dielectric, discarding the temporary structures that caused complexity without requiring recovery or removal of additional protective layers
2Reliability
If multiple sacrificial hardmask layers are used to protect dielectric during dual-damascene processing, then dielectric protection is improved, but manufacturing cost and turn-around time increase
Solution Approach 1:
The patent performs preliminary patterning of the dielectric material using sidewall image transfer before copper deposition. The mandrels are formed and their pattern is transferred to the dielectric in advance, creating a ready-to-fill template that eliminates the need for subsequent hardmask deposition and removal steps, thereby reducing manufacturing time while maintaining dielectric integrity
Solution Approach 2:
The patent extracts the protective function from separate hardmask layers and integrates it into the sidewall image transfer process itself. The dielectric is protected from damage by avoiding plasma etching and hardmask removal steps, while the patterning function is achieved through the self-aligned sidewall formation process
3Ease of manufacture
If plasma etching and multiple processing steps are used in dual-damascene integration, then interconnect structures can be formed, but process-induced dielectric damage increases
Solution Approach 1:
The patent converts the potentially harmful plasma etching process into a beneficial sidewall formation process. Instead of using plasma to etch away dielectric material (which causes damage), plasma is used to deposit conformal dielectric layers that form the sidewalls of the mandrels. This transforms a harmful etching step into a beneficial deposition step that protects rather than damages the dielectric
Solution Approach 2:
The patent replaces the mechanical removal process (plasma etching) with a deposition-based sidewall formation process. Instead of mechanically removing dielectric material to create patterns, the process uses conformal deposition to build sidewalls around mandrels, followed by mandrel removal to reveal the patterned dielectric structures
4Manufacturing precision
If many sacrificial films are used for patterning and protection in dual-damascene integration, then pattern fidelity is maintained, but manufacturing yield decreases due to defect introduction
Solution Approach 1:
The sidewall image transfer process is self-aligning, where the conformal deposition of dielectric material automatically creates sidewalls at precise locations relative to the mandrels. This self-service mechanism ensures pattern fidelity without requiring additional alignment steps or sacrificial layers, thereby improving manufacturing yield by reducing the number of opportunities for defect introduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies integration processes, reduces manufacturing costs, improves reliability, and enables the formation of fine-pitched interconnect structures not possible with traditional methods, while maintaining the performance gains of lower dielectric constant materials by minimizing plasma-induced damage and reducing the number of layers needed.
Implementation Method 1
conformally depositing an interlevel dielectric composition over the resist structures
Implementation Method 2
etching the interlevel dielectric composition to expose the resist structures
Implementation Method 3
filling the openings with an electrically conductive fill material
Data Source
AI summary
An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.