Sidewall Insulating Layers for Self-Aligned Vias in Resistance Change Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing of resistance change memory devices is hindered by the need for multiple photo engraving process (PEP) steps when resistance change elements and vias are processed in the same layer, making it difficult to reduce the number of PEP steps and increase costs.
Innovation Solution
The use of sidewall insulating layers with a thickness that allows self-alignment contact between them, forming holes for vias without PEP, and a laminate structure for the insulating layers to reduce the number of PEP steps required in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If resistance change elements and vias are provided in the same layer and independently processed, then both elements can be formed with proper alignment, but the number of photo engraving process (PEP) steps increases
Solution Approach 1:
The patent applies preliminary action by forming sidewall insulating layers on the resistance change elements before via formation. These pre-formed sidewall layers serve as alignment references that automatically define the via positions, eliminating the need for separate PEP steps for via alignment while ensuring precise positioning.
Solution Approach 2:
The sidewall insulating layers perform a dual function: they provide electrical insulation and simultaneously serve as self-aligned masks for via formation. The structure serves itself by using its own geometric features (sidewalls) to define the via locations, eliminating the need for external alignment processes.
2Manufacturing precision
If multiple PEP steps are used to process resistance change elements and vias independently, then proper patterning can be achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the via formation process with the resistance change element formation process by using the sidewall insulating layers as common structural features. Both the element patterning and via positioning are achieved through a single PEP step that defines the sidewall locations, combining what would traditionally require separate patterning operations.
Solution Approach 2:
The sidewall insulating layers serve multiple functions simultaneously: they provide electrical insulation between layers, define the via positions through their geometric configuration, and act as alignment references. This multi-functionality eliminates the need for dedicated alignment structures or additional PEP steps.
3Area of moving object
If sidewall insulating layers are made thin to maintain element density, then device integration is improved, but alignment accuracy for via formation deteriorates
Solution Approach 1:
The patent transitions from planar alignment methods to three-dimensional self-alignment by utilizing the vertical sidewalls of the insulating layers. The via positions are determined by the intersection of horizontal and vertical sidewalls in 3D space, providing precise alignment references even when the lateral dimensions are minimized for high density.
Data Source
AI summary
According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively.