Sidewall Interconnect Metallization for 3D IC Misregistration
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Solution Overview
Problem
As integrated circuits (ICs) shrink in size, the interconnection between different levels of metallization becomes increasingly challenging due to tight misregistration tolerances, especially in 3D stacked devices where lateral dimensions of transistors are in the range of 20-50 nm, making it difficult to reduce structural dimensions and maintain electrical connectivity.
Innovation Solution
The implementation of sidewall interconnect structures that contact the conductive sidewalls of metallization levels, providing a larger contact area and reducing electrical resistance, while a stop layer is used to ease registration requirements and avoid shorting between adjacent interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional interconnect structures are used in 3D stacked devices, then device density increases, but misregistration tolerances become extremely tight making electrical interconnection difficult
Solution Approach 1:
The patent transitions from planar interconnect geometry to three-dimensional sidewall interconnect structures. Conductive features extend vertically along the sidewalls of insulating regions, utilizing the vertical dimension to create interconnect pathways that are less sensitive to lateral misregistration between stacked device layers, thereby enabling reliable electrical connection despite tight misregistration tolerances in high-density 3D devices
2Quantity of substance
If lateral dimensions of transistors are reduced to 20-50 nm for 3D scaling, then device density increases, but structural dimensions become difficult to reduce further while maintaining electrical connectivity
Solution Approach 1:
The patent employs vertical sidewall interconnect structures that extend along the height of insulating regions rather than relying solely on lateral dimensions. This vertical orientation allows electrical connection to be established through the thickness direction of stacked layers, bypassing the limitation of further lateral dimension reduction and enabling continued device density scaling in the vertical dimension
Solution Approach 2:
The conductive sidewall interconnect structures are nested within or adjacent to the vertical sidewalls of insulating regions. This nested configuration allows the interconnect pathways to be integrated within the three-dimensional device architecture without requiring additional lateral space, enabling continued scaling as lateral dimensions approach physical limits
Data Source
AI summary
Interconnect metallization of an integrated circuit device includes a sidewall contact between conductive features. In a stacked device, a terminal interconnect of one device layer may intersect a sidewall of a conductive feature in another device layer or between two devices layers. In some examples, a terminal interconnect coupled to a gate, source, or drain terminal of a finFET in a vertically-stacked device may extend to a depth below a plane of the fin and intersect a sidewall of another interconnect, or another device terminal, that is in another plane of the stacked device. A stop layer below a top surface of the conductive feature may allow for sidewall contact while avoiding interconnect shorts.