Sidewall Mask for Strain Layer Formation in p-type MIS Transistors
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Solution Overview
Problem
Conventional semiconductor device fabrication processes for p-type MIS transistors require additional masks and excessive etching, leading to characteristic variations and increased procedure complexity, particularly when forming and removing insulating film masks.
Innovation Solution
The use of a sidewall forming film as a mask for forming strain layers in the p-type MIS transistor channel region eliminates the need for additional masks, reducing etching and active region thickness variations, and simplifies the fabrication process by integrating mask formation and removal steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an insulating film mask is formed and removed to create strain layers in p-type MIS transistor regions, then selective strain can be applied to p-type transistors, but excessive over-etching occurs and sidewall thickness is reduced
Solution Approach 1:
The patent introduces a sidewall film as an intermediary structure that serves dual purposes: it defines the strain layer formation region and protects the sidewall during etching. The sidewall film acts as a mediator between the etching process and the actual sidewall structure, preventing direct damage from over-etching while enabling precise strain layer formation in p-type transistor regions.
Solution Approach 2:
The sidewall film is formed in advance before the strain layer formation process. This preliminary action establishes protective structures and defines regions beforehand, preventing the need for subsequent mask formation and removal. The sidewall film is prepared with sufficient thickness to withstand the etching process without compromising the final sidewall dimensions.
2Ease of manufacture
If an insulating film mask is formed and removed for strain layer fabrication, then selective processing is achieved, but the number of fabrication procedures increases
Solution Approach 1:
The sidewall film serves multiple functions simultaneously: it acts as a region-defining structure, a protective layer during etching, and a template for strain layer formation. This multi-functionality eliminates the need for separate insulating film masks, reducing the number of fabrication steps while maintaining selective strain layer formation capability.
Solution Approach 2:
The patent merges the mask formation function with the sidewall formation process. Instead of creating separate insulating film masks for mask formation and removal steps, the sidewall film structure is utilized for both purposes, combining multiple functions into a single integrated process flow.
3Loss of substance
If excessive over-etching is performed to remove insulating film masks, then complete mask removal is achieved, but active region thickness is reduced and characteristics vary
Solution Approach 1:
The sidewall film is formed with a thickness that provides a cushion or buffer during the etching process. This preliminary cushioning layer protects the underlying active region from excessive etching, absorbing the etching aggressiveness while maintaining precise thickness control of the final structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances driving performance of semiconductor devices by minimizing characteristic variations and reducing the number of fabrication procedures, thereby improving the reliability and efficiency of the semiconductor device production.
Implementation Method 1
a SiGe layer 121 corresponding to a strain layer is epitaxially grown in the recess 100a
Implementation Method 2
a method in which a liner film is provided with compressive stress and a method in which an active region is provided with compressive stress by epitaxially growing a silicon germanium (SiGe) layer selectively on the active region
Data Source
AI summary
A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.