Sidewall Memory Gate Plug Connection for Semiconductor Integration
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Solution Overview
Problem
The MONOS non-volatile memory cells with a split gate structure face challenges in miniaturization and manufacturing yield due to defects in the pad electrode formation process, particularly due to mis-focusing and unevenness during photolithography, leading to increased resistance and reduced integration density.
Innovation Solution
A semiconductor device with a sidewall-shaped memory gate electrode and a cap insulating film is used, where the memory gate electrode is formed on the sidewall of the selection gate electrode, and a contact hole is formed in the interlayer insulating film to connect the memory gate electrode to a plug, eliminating the need for a pad electrode and reducing the power feeding region area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a pad electrode is formed in the conventional manner during photolithography, then electrical connection is achieved, but mis-focusing and unevenness occur leading to defects and increased resistance
Solution Approach 1:
The invention extracts and eliminates the pad electrode component from the conventional structure. By removing the pad electrode and its associated photolithography formation process, the source of mis-focusing and unevenness defects is eliminated, thereby improving manufacturing precision and electrical connection reliability simultaneously
Solution Approach 2:
The invention introduces a sidewall-shaped memory gate electrode as an intermediary structure that directly connects to the plug through a contact hole. This intermediary structure eliminates the need for the problematic pad electrode while maintaining electrical connection functionality, resolving the contradiction between manufacturing precision and reliability
2Area of moving object
If the power feeding region area is reduced for miniaturization, then integration density improves, but manufacturing yield decreases due to defects in pad electrode formation
Solution Approach 1:
By extracting and removing the pad electrode from the structure, the invention eliminates the defect-prone formation process while enabling further reduction of the power feeding region area. This resolves the contradiction by allowing miniaturization without sacrificing manufacturing yield
Solution Approach 2:
The invention transitions from a planar pad electrode structure to a three-dimensional sidewall-shaped memory gate electrode. This dimensional change allows electrical connection to be achieved through vertical contact holes rather than lateral pad formation, enabling area reduction while maintaining manufacturing reliability
Data Source
AI summary
In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.