Sidewall Metal Line Patterning for Sub-10nm Resistance
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Solution Overview
Problem
As metal line widths in semiconductor devices decrease below 10 nm, the cross-sectional area reduces, leading to increased resistance, and the use of seed layers further diminishes metal volume and increases resistance, highlighting deficiencies in traditional subtractive and damascene processes.
Innovation Solution
A method involving the formation of seed layers along only the first sidewall and upper surface of patterning structures, followed by the deposition of a metal layer, planarization to remove the metal and seed layers from the upper surface, and subsequent removal of patterning structures, ensuring the metal and seed layers remain along one sidewall, thereby optimizing metal line patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If metal line widths are reduced to below 10 nm, then device integration density is improved, but resistance increases due to reduced cross-sectional area
Solution Approach 1:
The patent transitions from planar metal line formation to three-dimensional metal line formation by depositing metal layers on the sidewalls of patterning structures. This vertical/dimensional approach allows the metal to extend along the sidewall surface, effectively increasing the conductive path area without increasing the horizontal line width, thus maintaining low resistance in sub-10nm lines.
Solution Approach 2:
The metal line is segmented into multiple deposition layers (first metal layer, second metal layer) deposited at different stages and orientations. The first metal layer is deposited on the sidewall, and the second metal layer is deposited after removing part of the patterning structure, creating a segmented but continuous conductive path that maintains electrical performance.
2Reliability
If seed layers are used in traditional damascene processes, then metal deposition is enabled, but metal volume is reduced and resistance increases
Solution Approach 1:
The patent extracts the seed layer function from the traditional damascene process by using the patterning structure sidewalls as the deposition substrate. The metal layers are deposited directly on the sidewalls without requiring a separate seed layer filling the trench, thereby eliminating the volume loss associated with traditional seed layer approaches.
Solution Approach 2:
The patterning structure sidewalls serve as an intermediary substrate that enables metal deposition without requiring a traditional seed layer. The sidewall surface provides the necessary nucleation sites for metal growth, replacing the function of the seed layer while preserving metal volume.
3Manufacturing precision
If subtractive processes are used for metal line formation, then patterning is achieved, but metal volume is lost and resistance increases
Solution Approach 1:
The patent inverts the traditional subtractive approach by using a constructive method where metal is deposited on the sidewalls of patterning structures. Instead of removing material to form the metal line, the metal is built up on the sidewall surface, preserving volume while achieving precise patterning through the sidewall geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and maintains metal volume by strategically placing the metal and seed layers along the sidewalls, enhancing the performance of semiconductor devices with narrower metal lines.
Implementation Method 1
forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures
Implementation Method 2
forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures
Implementation Method 3
forming a metal layer atop the seed layer
Implementation Method 4
forming a metal layer atop the seed layer
Data Source
AI summary
Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include a method may include providing a semiconductor device including plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop the seed layer, forming a fill material between each of the plurality of patterning structures, and removing the plurality of patterning structures.