Sidewall Resistor Structure for High Resistance Without Fine Lithography

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Solution Overview

Problem

The scaling down of semiconductor integrated circuits has outpaced the development of passive devices like resistors, which are limited by the resolution of back-end-of-line lithography processes, leading to increased costs and inefficiencies in forming resistors with high resistance.

Innovation Solution

A method for fabricating resistors alongside Metal-Insulator-Metal (MIM) capacitors, where the resistor is formed using a shared patterning process with the capacitor, allowing for the creation of resistors with small widths and high resistance without the need for high-resolution photolithography, thereby simplifying the fabrication process and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional photolithography processes are used to form resistors, then the existing fabrication process can be maintained, but the resolution limit prevents formation of resistors with sufficiently small widths for high resistance in advanced technology nodes

Engineering Contradiction:
Improveresistor width precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges the resistor formation process with the MIM capacitor formation process by using a shared patterning step. The same lithography pattern that defines the capacitor electrodes also defines the resistor geometry, eliminating the need for separate high-resolution lithography for resistors and simplifying the overall fabrication process while achieving the required small dimensions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patterning process serves multiple functions simultaneously: it patterns the MIM capacitor electrodes and also patterns the resistor structure. This multi-functional approach allows standard lithography resolution to meet the demanding尺寸 requirements for both device types without requiring advanced lithography techniques.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate patterning processes are used for resistors and MIM capacitors, then each device can be optimized independently, but the fabrication process complexity and cost increase

Engineering Contradiction:
Improvedevice performanceVSAvoidfabrication process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the patterning operations for resistors and MIM capacitors into a single lithography and etch sequence. The patterned layer serves as the electrode structure for MIM capacitors and simultaneously as the resistor structure, eliminating redundant process steps while maintaining device performance through proper material selection and geometric design.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If advanced lithography techniques are used to form small-width resistors, then high resistance can be achieved, but the fabrication cost and process complexity increase significantly

Engineering Contradiction:
Improveresistor widthVSAvoidfabrication cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

By merging the resistor and capacitor patterning into a single lithography step, the patent achieves the required small resistor widths using standard lithography resolution. The shared pattern ensures that the resistor dimensions are sufficiently small for high resistance without requiring expensive advanced lithography equipment or processes.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12027574B2Resistor structure
Publication Date: 2024.07.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12027574B2 patent drawing
  • US12027574B2 patent drawing
  • US12027574B2 patent drawing

AI summary

Semiconductor structures and methods of forming the same are provided. A method according to an embodiment includes forming a conductive feature and a first conductive plate over a substrate, conformally depositing a dielectric layer over the conductive feature and the first conductive plate, conformally depositing a conductive layer over the conductive feature and the first conductive plate, and patterning the conductive layer to form a second conductive plate over the first conductive plate and a resistor, the resistor includes a conductive line extending along a sidewall of the conductive feature. By employing the method, a high-resistance resistor may be formed along with a capacitor regardless of the resolution limit of, for example, lithography.