Sidewall Spacer Double Patterning for Uniform Line Widths
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Solution Overview
Problem
Current semiconductor processes face challenges in achieving uniform line widths and spacings during double patterning at advanced nodes due to etch bias effects, which affect the formation of fine structures like FinFET transistors, leading to non-uniform device performance and increased costs.
Innovation Solution
The method involves patterning a dummy layer and forming sidewall spacers at half-pitch lines, using a second photolithographic step to thin temporary spacer lines without fully removing them, and then etching these lines together with desired lines to transfer the pattern to final mask layers, eliminating mask loading effects and achieving uniform line widths and spacings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional double patterning approaches are used to achieve fine line spacing, then half-pitch resolution can be achieved, but etch bias effects cause non-uniform line widths and spacings
Solution Approach 1:
The patent applies preliminary action by forming dummy lines at the minimum photolithographic pitch before forming the final half-pitch pattern. These dummy lines are processed through sidewall spacer formation and selective removal to create a uniform etch mask pattern that compensates for etch bias effects, ensuring uniform line widths and spacings in the final device structures.
Solution Approach 2:
The patent changes the parameter of line density by introducing dummy lines at minimum pitch alongside the half-pitch lines. This parameter change ensures that all lines (both dummy and half-pitch) experience similar etch conditions and mask loading, thereby eliminating etch bias effects and achieving uniform line dimensions across the pattern.
2Productivity
If photolithography is used to pattern fine lines, then device density can be increased, but the theoretical resolution limits of photolithography equipment are exceeded
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into two separate steps: first forming dummy lines at the minimum photolithographic pitch, then forming sidewall spacers on these dummy lines to create the final half-pitch pattern. This segmentation allows the photolithography equipment to operate within its resolution capabilities while achieving finer final line spacing through the spacer formation step.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional sidewall spacer formation. By depositing spacer material on the vertical sidewalls of the dummy lines and then performing selective etching, the process achieves half-pitch resolution that exceeds the photolithography equipment's theoretical limits by utilizing the vertical dimension for pattern transfer.
3Area of stationary object
If outer lines are formed in a plurality of parallel lines using conventional approaches, then pattern coverage is achieved, but etch bias causes different width compared to inner lines
Solution Approach 1:
The patent applies homogeneity by ensuring that all lines in the pattern, including outer and inner lines, are surrounded by similar structures (dummy lines at minimum pitch). This homogeneous environment ensures that all lines experience identical etch conditions and mask loading, eliminating the etch bias that previously caused outer lines to have different widths compared to inner lines.
4Adaptability or versatility
If isolated lines are patterned using conventional approaches, then design flexibility is maintained, but etch bias non-uniformity occurs
Solution Approach 1:
The patent applies preliminary action by forming dummy lines at minimum pitch adjacent to isolated lines before performing the final pattern transfer. These dummy lines are processed through sidewall spacer formation and selective removal to create a uniform etch mask environment around isolated lines, ensuring they experience the same etch conditions as densely packed lines and achieving uniform line widths while maintaining design flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces or eliminates etch bias effects, resulting in more uniform device performance, improved yields, and lower costs by ensuring uniform line widths and spacings in integrated circuit devices, particularly for FinFET structures.
Implementation Method 1
patterning a plurality of dummy lines in the dummy layer by a first photolithographic process
Implementation Method 2
performing a second photolithographic patterning process to form a photoresist pattern
Implementation Method 3
etching the second mask layer and the first mask layer using the lines in the second mask layer as an etch mask
Implementation Method 4
etching the second mask layer and the first mask layer using the lines in the second mask layer as an etch mask
Implementation Method 5
depositing a dielectric material over the dummy lines; depositing a spacer material over the dummy lines
Data Source
AI summary
Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.